diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2022-06-08 21:30:26 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-23 12:16:50 +0000 |
| commit | 48f69da67b7db193bc1cacfd6c7f1a97553980a0 (patch) | |
| tree | e80b65d0e6c1b3522379e46f3e8e9c8b09375ee5 /src/soc/intel/apollolake/chip.c | |
| parent | ad07461a16adc4362088c80bcdafeea4fd4b2763 (diff) | |
soc/intel/apollolake: Enable SATA Power Optimisation
Enable PwrOptEnable FSP S UPD and hook it to the inverted value of
SataPwrOptimizeDisable to allow it to be disabled from the devicetree.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I056fd7b16dadb213b3326523b0c7943ce35b8dc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index ac8dfdf568..bbf0564906 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -734,6 +734,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) sizeof(silconfig->SataPortsEnable)); } + /* Sata Power Optimisation */ + silconfig->SataPwrOptEnable = !(cfg->SataPwrOptimizeDisable); + /* 8254 Timer */ bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); silconfig->Timer8254ClkSetting = use_8254; |