From 48f69da67b7db193bc1cacfd6c7f1a97553980a0 Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Wed, 8 Jun 2022 21:30:26 +0100
Subject: soc/intel/apollolake: Enable SATA Power Optimisation

Enable PwrOptEnable FSP S UPD and hook it to the inverted value of
SataPwrOptimizeDisable to allow it to be disabled from the devicetree.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I056fd7b16dadb213b3326523b0c7943ce35b8dc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
---
 src/soc/intel/apollolake/chip.c | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/soc/intel/apollolake/chip.c')

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index ac8dfdf568..bbf0564906 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -734,6 +734,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 			sizeof(silconfig->SataPortsEnable));
 	}
 
+	/* Sata Power Optimisation */
+	silconfig->SataPwrOptEnable = !(cfg->SataPwrOptimizeDisable);
+
 	/* 8254 Timer */
 	bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
 	silconfig->Timer8254ClkSetting = use_8254;
-- 
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