diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-03-18 11:19:38 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-03-23 14:24:44 +0100 |
| commit | eebe0e0db14476dde980896b8eb8a97129436af3 (patch) | |
| tree | 9a42d31c63f9aa0ead4c466d22a690e1406336cb /src/soc/intel/apollolake/bootblock | |
| parent | 7f8afe063139f6fc7076a3e4edf6093a953792dc (diff) | |
soc/intel/apollolake: utilize postcar phase/stage
The current Apollolake flow has its code executing out of
cache-as-ram for the pre-DRAM stages. This is different from
past platforms where they were just executing-in-place against
the memory-mapped SPI flash boot media. The implication is
that when cache-as-ram needs to be torn down one needs to be
executing out of DRAM since the act of cache-as-ram going
away means the code disappears out from under the processor.
Therefore load and use the postcar infrastructure to bootstrap
this process for tearing down cache-as-ram and subsequently
loading ramstage.
Change-Id: I856f4b992dd2609b95375767bfa4fe64a267d89e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14141
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/bootblock')
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/cache_as_ram.S | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index c81fe0a8e3..cc021dc3fe 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -16,8 +16,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> - -#define EVICT_CTL_MSR 0x2e0 +#include <soc/cpu.h> .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -96,7 +95,7 @@ clear_var_mtrr: mov %eax, %cr0 /* Disable cache eviction (setup stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr @@ -112,7 +111,7 @@ clear_var_mtrr: post_code(0x27) /* Disable cache eviction (run stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x2, %eax wrmsr |