diff options
| author | Furquan Shaikh <furquan@google.com> | 2016-06-14 09:35:04 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-06-15 18:47:34 +0200 |
| commit | 1f40ae2d746ec9a85770538a2e21620934331bd9 (patch) | |
| tree | d530b3151be2d0e923e683232cb8e4aa181205c1 /src/soc/intel/apollolake/acpi | |
| parent | d01f5a01e6daf0227bdee5eac1528882255285c1 (diff) | |
intel/apollolake: Correct the offsets in gnvs
Offsets start from 0 instead of 1. Fix this in the gnvs definitions.
BUG=chrome-os-partner:54342
Change-Id: Id6766a8766ef430d19ffcb801bfab43d38de37db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15180
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/acpi')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/globalnvs.asl | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 1799f315ab..3597788421 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -28,12 +28,12 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ Offset (0x00), - PCNT, 8, // 0x01 - Processor Count - PPCM, 8, // 0x02 - Max PPC State - LIDS, 8, // 0x03 - LID State - PWRS, 8, // 0x04 - AC Power State - DPTE, 8, // 0x05 - Enable DPTF - CBMC, 32, // 0x06 - 0x09 - Coreboot Memory Console + PCNT, 8, // 0x00 - Processor Count + PPCM, 8, // 0x01 - Max PPC State + LIDS, 8, // 0x02 - LID State + PWRS, 8, // 0x03 - AC Power State + DPTE, 8, // 0x04 - Enable DPTF + CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), |