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authorArthur Heymans <arthur@aheymans.xyz>2022-05-09 14:33:15 +0200
committerArthur Heymans <arthur@aheymans.xyz>2022-05-16 06:53:46 +0000
commit08769c6d1404c1be0333273d8b988544750ce87d (patch)
treeef37aeb920efea81b84ecf50c2ab990c09541b30 /src/soc/intel/apollolake/acpi
parent159520ed7881d1be2fdd02ee13040e8e21a9833c (diff)
soc/intel/*: Use SSDT to pass A4GB and A4GS
GNVS is more fragile as you need to keep struct elements in sync with ASL code. Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/acpi')
-rw-r--r--src/soc/intel/apollolake/acpi/globalnvs.asl2
-rw-r--r--src/soc/intel/apollolake/acpi/northbridge.asl3
2 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index 41f2409990..a56d2e106c 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -23,6 +23,4 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
SCDP, 8, // 0x29 - SD_CD GPIO portid
SCDO, 8, // 0x2A - GPIO pad offset relative to the community
UIOR, 8, // 0x2B - UART debug controller init on S3 resume
- A4GB, 64, // 0x2C - 0x33 Base of above 4GB MMIO Resource
- A4GS, 64, // 0x34 - 0x3B Length of above 4GB MMIO Resource
}
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index b05dc5603f..f8023bed9c 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -22,6 +22,9 @@ Device (MCHC)
}
}
+External (A4GS, IntObj)
+External (A4GB, IntObj)
+
/* Current Resource Settings */
Method (_CRS, 0, Serialized)
{