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authorVaibhav Shankar <vaibhav.shankar@intel.com>2016-08-15 11:32:26 -0700
committerAndrey Petrov <andrey.petrov@intel.com>2016-08-24 06:44:48 +0200
commit93f34e1a741044b13d1a666ff6ab0db2b85f74a5 (patch)
treeac5a2fcc2f85f5bfe10d7f7f15aa7cbb2c88912a /src/soc/intel/apollolake/acpi/southbridge.asl
parent1b5581c8d9a149bd28a74615bb416c7c7341d570 (diff)
soc/intel/apollolake: Add ASL methods for eMMC
Implement PS0 and PS3 methods to support eMMC power gate in S0ix suspend and resume. BUG=chrome-os-partner:53876 TEST=Suspend and Resume using 'echo freeze > /sys/power/state'. System should resume from S0ix. Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16233 Tested-by: build bot (Jenkins) Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/acpi/southbridge.asl')
-rw-r--r--src/soc/intel/apollolake/acpi/southbridge.asl3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 5b29abb557..391a531e4f 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -31,5 +31,8 @@
/* LPC */
#include "lpc.asl"
+/* eMMC */
+#include "scs.asl"
+
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>