diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2016-09-06 18:48:19 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-28 22:01:01 +0200 |
| commit | 28821dbb2261267462a7e9b0cc1c23b51af2d3ee (patch) | |
| tree | 98c2e5ea5d58afb11579c3bc4adeed895a576480 /src/soc/intel/apollolake/acpi/southbridge.asl | |
| parent | 9108680c1c17ec539bbba9525b6d9d62e57d296a (diff) | |
soc/intel/apollolake: Add pmc_ipc device support
A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver.
The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and
Punit Mailbox.
BRANCH=None
BUG=chrome-os-partner:57364
TEST=Boot up into OS successfully and check with dmesg to see the
driver has been loaded successfully without errors.
Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/16649
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/acpi/southbridge.asl')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/southbridge.asl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 1c10f1a5ed..f2b09c74eb 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -40,6 +40,9 @@ Scope (\_SB) #include "xhci.asl" +/* PMC IPC */ +#include "pmc_ipc.asl" + /* LPC */ #include "lpc.asl" |