diff options
| author | Hannah Williams <hannah.williams@intel.com> | 2016-06-08 17:39:37 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-24 19:11:21 +0200 |
| commit | 8ecd6f849c51bff6072f78e080b04a50735488b1 (patch) | |
| tree | 58e015c646e7e763bece8b7ff46c21ac010876a3 /src/soc/intel/apollolake/acpi/globalnvs.asl | |
| parent | 82ef8ada82bd63ea7ce61843189fd4ee5de45cb5 (diff) | |
soc/intel/apollolake: Include _PTS, _WAK and _SWS
Change-Id: I3400611095978421c7b35a7ea9c68b8571942ae9
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15138
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/acpi/globalnvs.asl')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/globalnvs.asl | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 3597788421..b2b7f5306b 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -34,6 +34,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PWRS, 8, // 0x03 - AC Power State DPTE, 8, // 0x04 - Enable DPTF CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console + PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index + GPEI, 64, // 0x11 - 0x18 - GPE Wake Source /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), |