soc/intel/apollolake: make use of common cbmem_top_chipset

This replaces apollolake's own implementation of cbmem_top_chipset and
selects the common code one.

Change-Id: I11d12a6c8414a98d38be8b0dbf6dc57cd2efc5d6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36618
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 4 deletions

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index ef81e32abd..24375b3599 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -28,7 +28,6 @@ romstage-y += gspi.c
 romstage-y += heci.c
 romstage-y += i2c.c
 romstage-y += uart.c
-romstage-y += memmap.c
 romstage-y += meminit.c
 ifeq ($(CONFIG_SOC_INTEL_GLK),y)
 romstage-y += meminit_util_glk.c
@@ -59,7 +58,6 @@ ramstage-y += gspi.c
 ramstage-y += heci.c
 ramstage-y += i2c.c
 ramstage-y += lpc.c
-ramstage-y += memmap.c
 ramstage-y += mmap_boot.c
 ramstage-y += uart.c
 ramstage-y += nhlt.c
@@ -73,7 +71,6 @@ ramstage-y += xdci.c
 ramstage-y += sd.c
 ramstage-y += xhci.c
 
-postcar-y += memmap.c
 postcar-y += mmap_boot.c
 postcar-y += spi.c
 postcar-y += i2c.c
@@ -86,7 +83,6 @@ verstage-y += car.c
 verstage-y += i2c.c
 verstage-y += gspi.c
 verstage-y += heci.c
-verstage-y += memmap.c
 verstage-y += mmap_boot.c
 verstage-y += uart.c
 verstage-y += pmutil.c