From 97012bd019896c589a4b736f17f5c1ad8f378924 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Mon, 4 Nov 2019 22:07:29 +0100 Subject: soc/intel/apollolake: make use of common cbmem_top_chipset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This replaces apollolake's own implementation of cbmem_top_chipset and selects the common code one. Change-Id: I11d12a6c8414a98d38be8b0dbf6dc57cd2efc5d6 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36618 Reviewed-by: Werner Zeh Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Makefile.inc | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/soc/intel/apollolake/Makefile.inc') diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index ef81e32abd..24375b3599 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -28,7 +28,6 @@ romstage-y += gspi.c romstage-y += heci.c romstage-y += i2c.c romstage-y += uart.c -romstage-y += memmap.c romstage-y += meminit.c ifeq ($(CONFIG_SOC_INTEL_GLK),y) romstage-y += meminit_util_glk.c @@ -59,7 +58,6 @@ ramstage-y += gspi.c ramstage-y += heci.c ramstage-y += i2c.c ramstage-y += lpc.c -ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += uart.c ramstage-y += nhlt.c @@ -73,7 +71,6 @@ ramstage-y += xdci.c ramstage-y += sd.c ramstage-y += xhci.c -postcar-y += memmap.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-y += i2c.c @@ -86,7 +83,6 @@ verstage-y += car.c verstage-y += i2c.c verstage-y += gspi.c verstage-y += heci.c -verstage-y += memmap.c verstage-y += mmap_boot.c verstage-y += uart.c verstage-y += pmutil.c -- cgit v1.2.3