diff options
| author | Uwe Poeche <uwe.poeche@siemens.com> | 2022-03-28 12:39:01 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-18 11:14:09 +0000 |
| commit | 539fd2ac5a0f510d8434d4cc8a597f092325b8c8 (patch) | |
| tree | 26b7b42ba97288d14ff218c4b49d2fc741a22d21 /src/soc/intel/apollolake/Kconfig | |
| parent | db9873b69c52cc1eac5bfef72228f071e303a78f (diff) | |
intel/common/block: Provide RAPL and min clock ratio switches in common
There are two APL specific config switches for RAPL and min. cpu clock
(APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches
could be used in future in other CPU platforms. Move them to common code
instead of having them just for one SOC.
Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings
(MSR0x610) do not change with this patch applied on mc_apl{1,4,5}
mainboard.
Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/apollolake/Kconfig')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index d23f31c20b..c5a3547e6a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -347,25 +347,6 @@ config CONSOLE_UART_BASE_ADDRESS default 0xddffc000 depends on INTEL_LPSS_UART_FOR_CONSOLE -config APL_SKIP_SET_POWER_LIMITS - bool - default n - help - Some Apollo Lake mainboards do not need the Running Average Power - Limits (RAPL) algorithm for a constant power management. - Set this config option to skip the RAPL configuration. - -config APL_SET_MIN_CLOCK_RATIO - bool - depends on !APL_SKIP_SET_POWER_LIMITS - default n - help - If the power budget of the mainboard is limited, it can be useful to - limit the CPU power dissipation at the cost of performance by setting - the lowest possible CPU clock. Enable this option if you need smallest - possible CPU clock. This setting can be overruled by the OS if it has an - p-state driver which can adjust the clock to its need. - # M and N divisor values for clock frequency configuration. # These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |