diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2022-06-20 08:09:29 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-22 18:34:33 +0000 |
| commit | 026f00476e11f6e9e53d19fba09d4d97c54e79cf (patch) | |
| tree | b66d8f4c4a76afec9e35dbc199b918d72588e6db /src/soc/intel/apollolake/Kconfig | |
| parent | 80503e3c54b34c5ceed5edf2d4f2454e57a10c33 (diff) | |
soc/intel/common/pch: Add a block specific to Apollo Lake
Add SOC_INTEL_COMMON_PCH_CLIENT which is specific to Apollo
Lake. This is used to select the options that Apollo Lake
requires, without the ones specific to a PCH as Apollo Lake
doesn't have a PCH.
This change also enables SOC_INTEL_COMMON_PCH_LOCKDOWN for
Apollo Lake.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I084a05f904a19f3b7e9a071636659670aa45bf3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/Kconfig')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 33 |
1 files changed, 10 insertions, 23 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 36bc631bb9..b2c224646f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -73,44 +73,23 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CAR - select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU - select SOC_INTEL_COMMON_BLOCK_DSP - select SOC_INTEL_COMMON_BLOCK_FAST_SPI - select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES - select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY - select SOC_INTEL_COMMON_BLOCK_GRAPHICS select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR - select SOC_INTEL_COMMON_BLOCK_ITSS - select SOC_INTEL_COMMON_BLOCK_I2C - select SOC_INTEL_COMMON_BLOCK_LPC - select SOC_INTEL_COMMON_BLOCK_LPSS - select SOC_INTEL_COMMON_BLOCK_PCR - select SOC_INTEL_COMMON_BLOCK_P2SB - select SOC_INTEL_COMMON_BLOCK_PMC + select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select SOC_INTEL_COMMON_BLOCK_SRAM - select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS - select SOC_INTEL_COMMON_BLOCK_TIMER - select SOC_INTEL_COMMON_BLOCK_TCO - select SOC_INTEL_COMMON_BLOCK_UART - select SOC_INTEL_COMMON_BLOCK_XDCI - select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_SMM - select SOC_INTEL_COMMON_BLOCK_SPI - select SOC_INTEL_COMMON_BLOCK_CSE - select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_RESET + select SOC_INTEL_INTEGRATED_SOUTHCLUSTER select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SOC_INTEL_NO_BOOTGUARD_MSR - select SOUTHBRIDGE_INTEL_COMMON_SMBUS select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_2017_BINDING @@ -277,6 +256,10 @@ config HEAP_SIZE hex default 0x8000 +config MAX_ROOT_PORTS + int + default 6 + config NHLT_DMIC_1CH_16B bool depends on ACPI_NHLT @@ -406,4 +389,8 @@ config BOOTBLOCK_IN_CBFS bool default n +config HAVE_PAM0_REGISTER + bool + default n + endif |