diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-09-27 19:26:20 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-10-12 18:25:35 +0000 |
| commit | d2fadda52a5df72dbaedeed5c7f1c94bedbfd898 (patch) | |
| tree | 83fd074be667a2a542e53636d4a8e165a9513a75 /src/soc/intel/alderlake | |
| parent | 87e0b5b1d741179e4ce63c9950ad91f265417283 (diff) | |
soc/intel: replace dt option PmTimerDisabled by Kconfig
Replace the dt option `PmTimerDisabled` with use of the Kconfig option
`USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer.
A default value representing the prior devicetree value was added to the
boards system76/{lemp10,galp5,darp7}, so this change will not alter
behaviour.
Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/finalize.c | 7 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index d3a41ee733..e98878f14e 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 270400b341..699626b767 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -286,7 +286,7 @@ struct soc_intel_alderlake_config { /* Enable C6 DRAM */ uint8_t enable_c6dram; - uint8_t PmTimerDisabled; + /* * SerialIO device mode selection: * PchSerialIoDisabled, diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index c821e25769..4ef572b5f6 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -50,7 +50,7 @@ static void pch_handle_sideband(config_t *config) static void pch_finalize(void) { - config_t *config; + config_t *config = config_of_soc(); /* TCO Lock down */ tco_lockdown(); @@ -58,13 +58,12 @@ static void pch_finalize(void) /* TODO: Add Thermal Configuration */ /* - * Disable ACPI PM timer based on dt policy + * Disable ACPI PM timer based on Kconfig * * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. * Disabling ACPI PM timer also switches off TCO */ - config = config_of_soc(); - if (config->PmTimerDisabled) + if (!CONFIG(USE_PM_ACPI_TIMER)) pmc_disable_acpi_timer(); pch_handle_sideband(config); |