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| author | Usha P <usha.p@intel.com> | 2022-01-17 20:06:38 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-25 16:10:46 +0000 |
| commit | 8f2df280e19f34a1c97adc29acee21a783e1e388 (patch) | |
| tree | 7fad3108749dbe6881a9f098b508cada02c144c9 /src/soc/intel/alderlake | |
| parent | 7760fe4645c55c2025a4fc9de0b205b8fd7031d3 (diff) | |
soc/intel/common: Include Alder Lake-N device IDs
Add Alder Lake-N System Agent, PCIE, UFS, IPU and CNVI device IDs.
Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548)
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0a383816f818b794cf1211766c27937b3b8daa31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/bootblock/report_platform.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/cpu.c | 2 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 01db34f3fd..5c695f29a3 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -47,6 +47,9 @@ static struct { { PCI_DEVICE_ID_INTEL_ADL_M_ID_2, "Alderlake-M" }, { PCI_DEVICE_ID_INTEL_ADL_N_ID_1, "Alderlake-N" }, { PCI_DEVICE_ID_INTEL_ADL_N_ID_2, "Alderlake-N" }, + { PCI_DEVICE_ID_INTEL_ADL_N_ID_3, "Alderlake-N" }, + { PCI_DEVICE_ID_INTEL_ADL_N_ID_4, "Alderlake-N" }, + }; static struct { diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index ed9c245234..b6dc898f4e 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -201,6 +201,8 @@ enum adl_cpu_type get_adl_cpu_type(void) const uint16_t adl_n_mch_ids[] = { PCI_DEVICE_ID_INTEL_ADL_N_ID_1, PCI_DEVICE_ID_INTEL_ADL_N_ID_2, + PCI_DEVICE_ID_INTEL_ADL_N_ID_3, + PCI_DEVICE_ID_INTEL_ADL_N_ID_4, }; const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT), |