diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-01-14 19:20:15 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-22 02:01:04 +0000 |
| commit | 23e2cde59791500c32765c5c53b37279347c1c95 (patch) | |
| tree | 8ef2801afe12b479917632acf053cad1b322a8fb /src/soc/intel/alderlake | |
| parent | 1587324a0dbcb9e3222aec6356de574dcc631747 (diff) | |
soc/intel/alderlake: Implement get_soc_cpu_type helper function
The patch implements get_soc_cpu_type() helper function which
determines whether the executing CPU is a small or a big core. This is
the SoC-specific callback that must be implemented for SoCs that select
SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID. It will be called from
set_cpu_type().
TEST=verified on Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Icd0d7e8a42c4b20d3e1d34998bca6321509df2d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/cpu.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 92ffe87043..ed9c245234 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -19,12 +19,18 @@ #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <intelblocks/msr.h> +#include <intelblocks/acpi.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> #include <types.h> +enum alderlake_model { + ADL_MODEL_P_M = 0x9A, + ADL_MODEL_N = 0xBE, +}; + bool cpu_soc_is_in_untrusted_mode(void) { msr_t msr; @@ -69,6 +75,21 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } +enum core_type get_soc_cpu_type(void) +{ + struct cpuinfo_x86 cpuinfo; + + if (cpu_is_hybrid_supported()) + return cpu_get_cpu_type(); + + get_fms(&cpuinfo, cpuid_eax(1)); + + if (cpuinfo.x86 == 0x6 && cpuinfo.x86_model == ADL_MODEL_N) + return CPUID_CORE_TYPE_INTEL_ATOM; + else + return CPUID_CORE_TYPE_INTEL_CORE; +} + /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { |