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| author | Jan Samek <jan.samek@siemens.com> | 2022-10-04 14:47:00 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2022-10-27 08:41:16 +0000 |
| commit | 1ed09082827c9fa12ed81dca02abb2b8d022577f (patch) | |
| tree | 33d3b477756fdea23436c0370e5b601eaaef1e63 /src/soc/intel/alderlake | |
| parent | 40d3409dab132eb292eb4d46064168731c575734 (diff) | |
mb/siemens/mc_apl2: Enable early POST through NC_FPGA
Enable early POST code output for this mainboard, using
the NC FPGA device on PCIe.
This requires the parent PCI bridge to be initialized early.
BUG=none
TEST=boot on siemens/mc_apl2 and observe whether the POST
codes coming from before FSP-M init are visible
Change-Id: Ice5fe26e11d0513e6bb0a20f1d8f0483d7b3dc6a
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/alderlake')
0 files changed, 0 insertions, 0 deletions