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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-08-24 09:20:14 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-26 18:23:24 +0000 |
| commit | d87af79ace16a499679d28ba3436950f9d9d090e (patch) | |
| tree | 5dd9ac8fd9eb2f5cb48fd6cbb339879266823bc3 /src/soc/intel/alderlake/pcie_rp.c | |
| parent | 30c6ca98381c3fa746aeeacdb37f77a5b9435750 (diff) | |
soc/intel/common/block: Add PAM locking function
Some FSPs provide a UPD to allow the bootloader to set the PAM lock bit
instead of the FSP, therefore add a function in the common code to do
this. Source: ADL & TGL FSP integration guides
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1d6642b496617b6e8ccda8a0aa6bfd88ea9dc3ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/pcie_rp.c')
0 files changed, 0 insertions, 0 deletions