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authorChris.Wang <chris.wang@amd.corp-partner.google.com>2022-12-28 17:07:48 +0800
committerMartin L Roth <gaumless@gmail.com>2023-01-04 07:15:10 +0000
commitad12b4f4404f7c3473dcf85960efe3f8a016f22b (patch)
treecc78ea24932c75081f09f975dc8b3c55eabcbb57 /src/soc/intel/alderlake/p2sb.c
parente66fcb87fed9b25be5e35eef05133ef7596edd46 (diff)
soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimization
Add the UPD dxio_tx_vboost_enable for PCIe optimization. It will impact the PCIe signal integrity, need to double-confirm the SI result after enabling this setting. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/p2sb.c')
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