diff options
| author | Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> | 2023-06-06 20:13:17 +0800 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-06-12 04:04:06 +0000 |
| commit | 623e3a3963ea20881ba2d3096f873db81f1acdb7 (patch) | |
| tree | 61a630c16900b00355f5b191c4cfa18148f42118 /src/soc/intel/alderlake/meminit.c | |
| parent | e7bedaf364cf578b22eb2977bbd2653bd83f85e1 (diff) | |
mb/google/nissa/var/joxer: Configure the external V1p05/Vnn/VnnSx rails
This patch configures external V1p05/Vnn/VnnSx rails for Joxer
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide
BUG=b:285477026
TEST=Verified all the UPD values are updated with these configs.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I78d2a885d577f6c1a89ab74c0da7b6544322c0d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/soc/intel/alderlake/meminit.c')
0 files changed, 0 insertions, 0 deletions