diff options
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2022-05-06 10:27:50 +0530 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2022-05-16 04:57:45 +0000 |
| commit | afe840957cc3e5df47e7a91815fac5ae95af52e1 (patch) | |
| tree | 4fe94dd4bd986550395c6ccf8a7c9c6de90949f5 /src/soc/intel/alderlake/include | |
| parent | 37ffdf3d5ccf6601b68811ff233bb377d4417838 (diff) | |
soc/inte/*/gpio; Add GPE_EN and GPE_STS register definition
coreboot needs to set GPE_EN bit for the GPIOs which are wake capable
from s0ix/sleep. Due to GPIO locking mechanism, coreboot/OS will not
be able to write GPE_EN register post GPIO has been locked.
This patch adds support in SoC code to provide correct offset for
GPE_EN and GPE_STS registers to the common code.
Plan is to use this offsets to set GPE_EN bits before GPIO locking
in coreboot which will be part of subsequent CL.
BUG=b:222375516
BRANCH=firmware-brya-14505.B
TEST=Check if code compiles for Brya and correct offset values are printed.
Change-Id: I6b813b30b8b360f8eccbf539b57387310e380560
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/alderlake/include')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/gpio_defs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/gpio_defs.h b/src/soc/intel/alderlake/include/soc/gpio_defs.h index 86021672f4..de520c9884 100644 --- a/src/soc/intel/alderlake/include/soc/gpio_defs.h +++ b/src/soc/intel/alderlake/include/soc/gpio_defs.h @@ -344,6 +344,8 @@ #define HOSTSW_OWN_REG_0 0xb0 #define GPI_INT_STS_0 0x100 #define GPI_INT_EN_0 0x110 +#define GPI_GPE_STS_0 0x140 +#define GPI_GPE_EN_0 0x160 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x700 |