diff options
| author | Usha P <usha.p@intel.com> | 2021-11-30 11:27:38 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-12-03 21:29:37 +0000 |
| commit | 78c9b678d74ae9acd9ce04136706c7915cd34097 (patch) | |
| tree | d131317e6aa618199afb44c58063fca393914527 /src/soc/intel/alderlake/include | |
| parent | 7e7cc1a8c9a87e33bd772e8526734c7a82ec2db7 (diff) | |
soc/intel/alderlake: Add support for ADL-N PCH
Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to
specify the correct amount of PCIe I/O.
Document number 645550 indicates that Alder Lake-N has 12 PCH root ports
and no CPU root ports.
Document number 645548 indicates ADL-N has 5 clock sources and 5 clock
request signals.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake/include')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/bootblock.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h index 059568d09b..ce2e42e6b2 100644 --- a/src/soc/intel/alderlake/include/soc/bootblock.h +++ b/src/soc/intel/alderlake/include/soc/bootblock.h @@ -4,6 +4,7 @@ #define _SOC_ALDERLAKE_BOOTBLOCK_H_ #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) + \ + CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + \ CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) != 1 #error "Please select exactly one PCH type" #endif |