diff options
| author | Michał Kopeć <michal.kopec@3mdeb.com> | 2022-04-08 11:28:45 +0200 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-06-30 13:54:48 +0000 |
| commit | 75a49fe856830d97baf882caf35962577d7cba5e (patch) | |
| tree | 958e0b196872d728bcae2d973c9ebe34dc5bbe81 /src/soc/intel/alderlake/fsp_params.c | |
| parent | a08f509cc537e3608a41930592a6cb9ea81df6ab (diff) | |
soc/intel/alderlake: add chipset devicetree for ADL-S
Add chipset devicetree and power limits for AlderLake-S platform.
Based on Intel docs #619501, #619362 and #626343.
Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/intel/alderlake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index e82607c1ec..864367f207 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -599,6 +599,11 @@ static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, s_cfg->PavpEnable = CONFIG(PAVP); } +WEAK_DEV_PTR(tcss_usb3_port1); +WEAK_DEV_PTR(tcss_usb3_port2); +WEAK_DEV_PTR(tcss_usb3_port3); +WEAK_DEV_PTR(tcss_usb3_port4); + static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { |