soc/intel/alderlake: Refactor PCIE port config

Refactor PCIE port config structure. Make it easier to map from
schematic. We don't have to convert the PCIE ports RP number and
CLK source in devicetree. All the convert will be done by SoC level.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

1 files changed, 11 insertions, 9 deletions

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 35f7a3c2e2..6e6f1af94f 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -15,6 +15,7 @@
 #include <soc/gpio_soc_defs.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/pci_devs.h>
+#include <soc/pcie.h>
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
 #include <string.h>
@@ -93,6 +94,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	const struct microcode *microcode_file;
 	size_t microcode_len;
 	FSP_S_CONFIG *params = &supd->FspsConfig;
+	uint32_t enable_mask;
 
 	struct device *dev;
 	struct soc_intel_alderlake_config *config;
@@ -270,19 +272,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	/* Enable Hybrid storage auto detection */
 	params->HybridStorageMode = config->HybridStorageMode;
 
+	enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
 	for (i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) {
+		if (!(enable_mask & BIT(i)))
+			continue;
+		const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i];
 		params->PcieRpL1Substates[i] =
-			get_l1_substate_control(config->PcieRpL1Substates[i]);
-		params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i];
-		params->PcieRpAdvancedErrorReporting[i] =
-		config->PcieRpAdvancedErrorReporting[i];
-		params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
+				get_l1_substate_control(rp_cfg->PcieRpL1Substates);
+		params->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR);
+		params->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
+		params->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG);
+		params->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
 	}
 
-	/* Enable ClkReqDetect for enabled port */
-	memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
-		sizeof(config->PcieRpClkReqDetect));
-
 	params->PmSupport = 1;
 	params->Hwp = 1;
 	params->Cx = 1;