diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-07-19 15:35:47 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-10 19:38:46 +0000 |
| commit | e2b8f30beeb1b63e1b94dccc1a96bed5c9a2c63e (patch) | |
| tree | a95616939edb85010ad7dc2d679daa6518d61b15 /src/soc/intel/alderlake/cpu.c | |
| parent | 6cf79d9d14aa6be9bc5594dcf4040da8cbb87544 (diff) | |
soc/intel/alderlake: Set LpmStateEnableMask UPD
Use the get_supported_lpm_states() function to set the respective FSP
UPD.
TEST=with patchtrain on brya0,
/sys/kernel/debug/pmc_core/substate_requirements shows only the
substates that are applicable to the design (S0i2.0, S0i3.0).
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5bb8b3671e78c5f2706db2d3a21b25cf90a14275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/cpu.c')
| -rw-r--r-- | src/soc/intel/alderlake/cpu.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index c5dc804c0f..2f1ac8ea0c 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -188,3 +188,18 @@ enum adl_cpu_type get_adl_cpu_type(void) return ADL_UNKNOWN; } + +uint8_t get_supported_lpm_mask(void) +{ + enum adl_cpu_type type = get_adl_cpu_type(); + switch (type) { + case ADL_M: /* fallthrough */ + case ADL_P: + return LPM_S0i2_0 | LPM_S0i3_0; + case ADL_S: + return LPM_S0i2_0 | LPM_S0i2_1; + default: + printk(BIOS_ERR, "Unknown ADL CPU type: %d\n", type); + return 0; + } +} |