diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-08-31 17:01:02 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-03 16:14:28 +0000 |
| commit | eaf87a9d6051eafcf4e4c315d9fa1844ab6ee45f (patch) | |
| tree | 110950d1ebc96d572bd66c8a6ded83cbc5a8a88c /src/soc/intel/alderlake/chipset.cb | |
| parent | dc0e066406d2ac36c83d4abd871f20e3121f7cc5 (diff) | |
soc/intel/alderlake: set power limits dynamically for thermal
Set power limit values dynamically based on CPU TDP and PCI ID of SKU.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57035
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/chipset.cb')
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index eff64f17d4..c89fe6ae06 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -2,30 +2,36 @@ chip soc/intel/alderlake device cpu_cluster 0 on end - register "power_limits_config[ADL_P_POWER_LIMITS_282_CORE]" = "{ + register "power_limits_config[ADL_P_282_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 55, .tdp_pl4 = 123, }" - register "power_limits_config[ADL_P_POWER_LIMITS_482_CORE]" = "{ + register "power_limits_config[ADL_P_482_CORE]" = "{ .tdp_pl1_override = 28, .tdp_pl2_override = 64, .tdp_pl4 = 140, }" - register "power_limits_config[ADL_P_POWER_LIMITS_682_CORE]" = "{ + register "power_limits_config[ADL_P_682_28W_CORE]" = "{ + .tdp_pl1_override = 28, + .tdp_pl2_override = 64, + .tdp_pl4 = 140, + }" + + register "power_limits_config[ADL_P_682_45W_CORE]" = "{ .tdp_pl1_override = 45, .tdp_pl2_override = 115, .tdp_pl4 = 215, }" - register "power_limits_config[ADL_M_POWER_LIMITS_282_CORE]" = "{ + register "power_limits_config[ADL_M_282_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 45, }" - register "power_limits_config[ADL_M_POWER_LIMITS_242_CORE]" = "{ + register "power_limits_config[ADL_M_242_CORE]" = "{ .tdp_pl1_override = 9, .tdp_pl2_override = 30, .tdp_pl4 = 68, |