diff options
| author | Simon Yang <simon1.yang@intel.com> | 2024-05-28 17:41:49 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-29 12:30:29 +0000 |
| commit | 40867e7b47077511f4d24585fd4f5d4a8d8de5d7 (patch) | |
| tree | d10500eb4bc5ec981f91debcd2de92d2138d48cd /src/soc/intel/alderlake/chip.h | |
| parent | ced2a017f2362af37d27126ef65b8894377df4d8 (diff) | |
soc/intel/alderlake: Add Vccin Aux Imon Iccmax setting
According to RDC#646929 Power Map, there are two expected values of
VccInAuxImonIccImax and the value has to align with HW design.
But in current code, vccin_aux_imon_iccmax is hard code to 27000 (27A),
hence, provide a config for projects modification.
BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST=Modify the register and add a printk to output a debug message
to observe whether the value is changing as expected.
Change-Id: I0651f0eb8a5c32b27c524e43bbf6f2a184b95657
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/chip.h')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index b58b244607..ec6c0f5483 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -777,6 +777,16 @@ struct soc_intel_alderlake_config { * Set this to 0 in order to disable hwp scalability tracking. */ bool enable_hwp_scalability_tracking; + + /* + * (ADL-N/TWL only) Vccin Aux Imon Iccmax + * Defaults to 27000 (27A), the value has to align with HW design. + * Recommended value: 25000 (PD_TIER_PREMIUM) or 27000 (PD_TIER_VOLUME) + */ + enum { + PD_TIER_PREMIUM = 25000, + PD_TIER_VOLUME = 27000 + } vccin_aux_imon_iccmax; }; typedef struct soc_intel_alderlake_config config_t; |