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| author | Casper Chang <casper_chang@wistron.corp-partner.google.com> | 2021-11-15 18:05:18 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-17 14:32:48 +0000 |
| commit | d16a085110d42e28d273e94f96b60ef39c4bb0c2 (patch) | |
| tree | 590573def09a2a6175cdee4699b144e3a0f3e9ad /src/soc/intel/alderlake/acpi | |
| parent | 5c3d12eaeeb76a56c7634f700674e89fc360e007 (diff) | |
mb/google/brya/variants/primus: Correct SSD power sequence
SSD sometimes can't be detected in in warm/cold boot stress.
M.2 spec describes SSD_PERST# should be sequenced after power enable.
BUG=b:199967106
TEST=SSD was always discovered in warm/cold boot stress.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake/acpi')
0 files changed, 0 insertions, 0 deletions