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author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-07-12 13:22:09 +0200 |
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committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-08-03 09:55:19 +0000 |
commit | 01025d3ae78e02192d389f22abd36747e3d8c63b (patch) | |
tree | 521885cf47da33826a55b608ae690d1d1a16620f /src/soc/intel/alderlake/acpi/sata.asl | |
parent | ce7d818254a861bfb6c6911342b2db13cb484cfa (diff) |
soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO
Only the headers on Intel FSP repository have the CnviWifiCore
present. Options guarded for RPL like: DisableDynamicTccoldHandshake
or EnableFastVmode and IccLimit is also supported by all public FSPs
(except ADL-N for the handshake).
Options like LowerBasicMemTestSize and DisableSagvReorder have to be
guarded when FSP_USE_REPO is not selected, as publci FSPs do not have
these options.
Use FSP_USE_REPO instead of/in addition to SOC_INTEL_RAPTORLAKE
as dependency on the guarded UPDs to make them available for FSPs
that support them as well. Also prioritize the headers from FSP repo
over vendorcode headers if FSP_USE_REPO is selected.
Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Diffstat (limited to 'src/soc/intel/alderlake/acpi/sata.asl')
0 files changed, 0 insertions, 0 deletions