diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-04-20 12:52:51 +0200 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-06-28 09:16:54 +0000 |
| commit | f422ed898dfaaadf69409c1a79ffb5157f8897d6 (patch) | |
| tree | d91702d2ab9cb4a043fca85710782265e2861434 /src/soc/intel/alderlake/acpi/pcie.asl | |
| parent | e28c71802d338ecc831776ed3d963a3cfc8ad302 (diff) | |
soc/intel/alderlake/acpi: Add ADL-S devices
Add PCIe Root Ports, USB ports and SIO devices for ADL-S chipset.
Add IRQ routing tables for PCIe Root ports up to 28th.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I508fa1396b07f38801bcf50cdfdc876356d7ae9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63785
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/acpi/pcie.asl')
| -rw-r--r-- | src/soc/intel/alderlake/acpi/pcie.asl | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/src/soc/intel/alderlake/acpi/pcie.asl b/src/soc/intel/alderlake/acpi/pcie.asl index f2123aa613..f1ae090524 100644 --- a/src/soc/intel/alderlake/acpi/pcie.asl +++ b/src/soc/intel/alderlake/acpi/pcie.asl @@ -54,7 +54,7 @@ Method (IRQM, 1, Serialized) { Switch (ToInteger (Arg0)) { - Case (Package () { 1, 5, 9, 13 }) { + Case (Package () { 1, 5, 9, 13, 17, 21, 25 }) { If (PICM) { Return (IQAA) } Else { @@ -62,7 +62,7 @@ Method (IRQM, 1, Serialized) { } } - Case (Package () { 2, 6, 10, 14 }) { + Case (Package () { 2, 6, 10, 14, 18, 22, 26 }) { If (PICM) { Return (IQBA) } Else { @@ -70,7 +70,7 @@ Method (IRQM, 1, Serialized) { } } - Case (Package () { 3, 7, 11, 15 }) { + Case (Package () { 3, 7, 11, 15, 19, 23, 27 }) { If (PICM) { Return (IQCA) } Else { @@ -78,7 +78,7 @@ Method (IRQM, 1, Serialized) { } } - Case (Package () { 4, 8, 12, 16 }) { + Case (Package () { 4, 8, 12, 16, 20, 24, 28 }) { If (PICM) { Return (IQDA) } Else { @@ -300,6 +300,11 @@ Device (RP12) } } +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#include "pcie_pch_s.asl" +#endif + + #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) Device (PEG0) { |