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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-04-07 15:09:19 +0200 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-04-11 08:48:15 +0000 |
| commit | dccfb8a2158287be48522f9f70fd3e83b84c671f (patch) | |
| tree | eab3b873b48ae8661535b27b8c58e1ca6dfc3832 /src/soc/intel/alderlake/Kconfig | |
| parent | f3cc03b137cbceb144a78e709ae66fa1ac314b91 (diff) | |
soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S
According to Intel DOC #630603 P2SB BAR must be at 0xe0000000 for
PCH-S.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake/Kconfig')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b63162465f..35fd2f710f 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -251,6 +251,7 @@ config SMM_RESERVED_SIZE config PCR_BASE_ADDRESS hex + default 0xe0000000 if SOC_INTEL_ALDERLAKE_PCH_S default 0xfd000000 help This option allows you to select MMIO Base Address of sideband bus. |