Remove imgtec/pistachio SoC

After removing urara no board still uses this SoC, and there are no
plans to add any in the future (I'm not sure if the chip really exists
tbh...).

Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 0 insertions, 694 deletions

diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h
deleted file mode 100644
index 27ba6d6c20..0000000000
--- a/src/soc/imgtec/pistachio/include/soc/clocks.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Imagination Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __SOC_IMGTEC_PISTACHIO_CLOCKS_H__
-#define __SOC_IMGTEC_PISTACHIO_CLOCKS_H__
-
-#include <stdint.h>
-
-/* Functions for PLL setting */
-int sys_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback);
-int mips_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback);
-
-/* Peripheral divider setting */
-void system_clk_setup(u8 divider);
-void mips_clk_setup(u8 divider1, u8 divider2);
-void uart1_clk_setup(u8 divider1, u16 divider2);
-void i2c_clk_setup(u8 divider1, u16 divider2, u8 interface);
-int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel);
-void rom_clk_setup(u8 divider);
-void eth_clk_setup(u8 mux, u8 divider);
-void setup_clk_gate_defaults(void);
-enum {
-	CLOCKS_OK = 0,
-	PLL_TIMEOUT = -1,
-	USB_TIMEOUT = -2,
-	USB_VBUS_FAULT = -3
-};
-
-#endif
diff --git a/src/soc/imgtec/pistachio/include/soc/cpu.h b/src/soc/imgtec/pistachio/include/soc/cpu.h
deleted file mode 100644
index c22dceba45..0000000000
--- a/src/soc/imgtec/pistachio/include/soc/cpu.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Imagination Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __SOC_IMGTEC_DANUBE_CPU_H__
-#define __SOC_IMGTEC_DANUBE_CPU_H__
-
-#include <device/mmio.h>
-
-#define IMG_SPIM0_BASE_ADDRESS	0xB8100F00
-#define IMG_SPIM1_BASE_ADDRESS	0xB8101000
-
-/*
- * This register holds the FPGA image version
- * If we're not working on the FPGA this will be 0
- */
-#define PRIMARY_FPGA_VERSION		0xB8149060
-#define IMG_PLATFORM_ID()		read32_x(PRIMARY_FPGA_VERSION)
-#define IMG_PLATFORM_ID_FPGA		0xD1400003 /* Last FPGA image */
-#define IMG_PLATFORM_ID_SILICON		0
-
-#endif
diff --git a/src/soc/imgtec/pistachio/include/soc/ddr_init.h b/src/soc/imgtec/pistachio/include/soc/ddr_init.h
deleted file mode 100644
index d8b5b19bae..0000000000
--- a/src/soc/imgtec/pistachio/include/soc/ddr_init.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Imagination Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __SOC_IMGTEC_PISTACHIO_DDR_INIT_H__
-#define __SOC_IMGTEC_PISTACHIO_DDR_INIT_H__
-
-#define DDR_TIMEOUT			-1
-
-int init_ddr2(void);
-int init_ddr3(void);
-
-#endif
diff --git a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h b/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h
deleted file mode 100644
index eab5b3a142..0000000000
--- a/src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Imagination Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __SOC_IMGTEC_PISTACHIO_DDR_PRIVATE_REG_H__
-#define __SOC_IMGTEC_PISTACHIO_DDR_PRIVATE_REG_H__
-
-#include <device/mmio.h>
-#include <timer.h>
-
-#define MAX_WAIT_MICROS			100000
-
-#define TOPLEVEL_REGS			0xB8149000
-
-#define DDR_CTRL_OFFSET			(0x0020)
-#define DDR_CLK_EN_MASK			(0x00000002)
-#define DDR_CLK_EN_SHIFT		(1)
-#define DDR_CLK_EN_LENGTH		(1)
-
-#define DDR_PCTL			0xB8180000
-#define DDR_PCTL_SCFG_OFFSET		(0x0000)
-#define DDR_PCTL_SCTL_OFFSET		(0x0004)
-#define DDR_PCTL_STAT_OFFSET		(0x0008)
-#define DDR_PCTL_MCMD_OFFSET		(0x0040)
-#define DDR_PCTL_POWCTL_OFFSET		(0x0044)
-#define DDR_PCTL_POWSTAT_OFFSET		(0x0048)
-#define DDR_PCTL_CMDTSTAT_OFFSET	(0x004C)
-#define DDR_PCTL_CMDTSTATEN_OFFSET	(0x0050)
-#define DDR_PCTL_MCFG1_OFFSET		(0x007C)
-#define DDR_PCTL_MCFG_OFFSET		(0x0080)
-#define DDR_PCTL_MSTAT_OFFSET		(0x0088)
-#define DDR_PCTL_DTUAWDT_OFFSET		(0x00B0)
-#define DDR_PCTL_TOGCNT1U_OFFSET	(0x00C0)
-#define DDR_PCTL_TINIT_OFFSET		(0x00C4)
-#define DDR_PCTL_TRSTH_OFFSET		(0x00C8)
-#define DDR_PCTL_TOGG_CNTR_100NS_OFFSET	(0x00CC)
-#define DDR_PCTL_TREFI_OFFSET		(0x00D0)
-#define DDR_PCTL_TMRD_OFFSET		(0x00D4)
-#define DDR_PCTL_TRFC_OFFSET		(0x00D8)
-#define DDR_PCTL_TRP_OFFSET		(0x00DC)
-#define DDR_PCTL_TRTW_OFFSET		(0x00E0)
-#define DDR_PCTL_TAL_OFFSET		(0x00E4)
-#define DDR_PCTL_TCL_OFFSET		(0x00E8)
-#define DDR_PCTL_TCWL_OFFSET		(0x00EC)
-#define DDR_PCTL_TRAS_OFFSET		(0x00F0)
-#define DDR_PCTL_TRC_OFFSET		(0x00F4)
-#define DDR_PCTL_TRCD_OFFSET		(0x00F8)
-#define DDR_PCTL_TRRD_OFFSET		(0x00FC)
-#define DDR_PCTL_TRTP_OFFSET		(0x0100)
-#define DDR_PCTL_TWR_OFFSET		(0x0104)
-#define DDR_PCTL_TWTR_OFFSET		(0x0108)
-#define DDR_PCTL_TEXSR_OFFSET		(0x010C)
-#define DDR_PCTL_TXP_OFFSET		(0x0110)
-#define DDR_PCTL_TXPDLL_OFFSET		(0x0114)
-#define DDR_PCTL_TZQCS_OFFSET		(0x0118)
-#define DDR_PCTL_TDQS_OFFSET		(0x0120)
-#define DDR_PCTL_TCKE_OFFSET		(0x012C)
-#define DDR_PCTL_TMOD_OFFSET		(0x0130)
-#define DDR_PCTL_TZQCL_OFFSET		(0x0138)
-#define DDR_PCTL_TCKESR_OFFSET		(0x0140)
-#define DDR_PCTL_TREFI_MEM_DDR3_OFFSET	(0x0148)
-#define DDR_PCTL_DTUWACTL_OFFSET	(0x0200)
-#define DDR_PCTL_DTURACTL_OFFSET	(0x0204)
-#define DDR_PCTL_DTUCFG_OFFSET		(0x0208)
-#define DDR_PCTL_DTUECTL_OFFSET		(0x020C)
-#define DDR_PCTL_DTUWD0_OFFSET		(0x0210)
-#define DDR_PCTL_DTUWD1_OFFSET		(0x0214)
-#define DDR_PCTL_DTUWD2_OFFSET		(0x0218)
-#define DDR_PCTL_DTUWD3_OFFSET		(0x021C)
-#define DDR_PCTL_DFIODTCFG_OFFSET	(0x0244)
-#define DDR_PCTL_DFIODTCFG1_OFFSET	(0x0248)
-#define DDR_PCTL_DFITPHYWRDATA_OFFSET	(0x0250)
-#define DDR_PCTL_DFIWRLAT_OFFSET	(0x0254)
-#define DDR_PCTL_DFITRDDATAEN_OFFSET	(0x0260)
-#define DDR_PCTL_DFITPHYRDLAT_OFFSET	(0x0264)
-#define DDR_PCTL_DFIUPDCFG_OFFSET	(0x0290)
-#define DDR_PCTL_DFISTAT0_OFFSET	(0x02C0)
-#define DDR_PCTL_DFISTCFG0_OFFSET	(0x02C4)
-#define DDR_PCTL_DFISTCFG1_OFFSET	(0x02C8)
-#define DDR_PCTL_DFISTCFG2_OFFSET	(0x02D8)
-#define DDR_PCTL_DFILPCFG0_OFFSET	(0x02F0)
-#define DDR_PCTL_PCFG0_OFFSET		(0x0400)
-#define DDR_PCTL_CCFG_OFFSET		(0x0480)
-#define DDR_PCTL_DCFG_OFFSET		(0x0484)
-#define DDR_PCTL_CCFG1_OFFSET		(0x048C)
-
-#define DDR_PHY				0xB8180800
-#define DDRPHY_PIR_OFFSET		(0x0004)
-#define DDRPHY_PGCR_OFFSET		(0x0008)
-#define DDRPHY_PGSR_OFFSET		(0x000C)
-#define DDRPHY_DLLGCR_OFFSET		(0x0010)
-#define DDRPHY_PTR0_OFFSET		(0x0018)
-#define DDRPHY_PTR1_OFFSET		(0x001C)
-#define DDRPHY_DXCCR_OFFSET		(0x0028)
-#define DDRPHY_DSGCR_OFFSET		(0x002C)
-#define DDRPHY_DCR_OFFSET		(0x0030)
-#define DDRPHY_DTPR0_OFFSET		(0x0034)
-#define DDRPHY_DTPR1_OFFSET		(0x0038)
-#define DDRPHY_DTPR2_OFFSET		(0x003C)
-#define DDRPHY_MR_OFFSET		(0x0040)
-#define DDRPHY_EMR_OFFSET		(0x0044)
-#define DDRPHY_EMR2_OFFSET		(0x0048)
-#define DDRPHY_EMR3_OFFSET		(0x004C)
-#define DDRPHY_DTAR_OFFSET		(0x0054)
-#define DDRPHY_BISTRR_OFFSET		(0x0100)
-#define DDRPHY_BISTWCR_OFFSET		(0x010C)
-#define DDRPHY_BISTAR0_OFFSET		(0x0114)
-#define DDRPHY_BISTAR1_OFFSET		(0x0118)
-#define DDRPHY_BISTAR2_OFFSET		(0x011C)
-#define DDRPHY_BISTUDPR_OFFSET		(0x0120)
-#define DDRPHY_BISTGSR_OFFSET		(0x0124)
-#define DDRPHY_ZQ0CR0_OFFSET		(0x0180)
-#define DDRPHY_ZQ1CR0_OFFSET		(0x0190)
-
-#define DDR_TIMEOUT_VALUE_US		100000
-
-static int wait_for_completion(u32 reg, u32 exp_val)
-{
-	struct stopwatch sw;
-
-	stopwatch_init_usecs_expire(&sw, DDR_TIMEOUT_VALUE_US);
-	while (read32_x(reg) != exp_val) {
-		if (stopwatch_expired(&sw))
-			return DDR_TIMEOUT;
-	}
-	return 0;
-}
-
-#endif
diff --git a/src/soc/imgtec/pistachio/include/soc/gpio.h b/src/soc/imgtec/pistachio/include/soc/gpio.h
deleted file mode 100644
index 64f2e27c8b..0000000000
--- a/src/soc/imgtec/pistachio/include/soc/gpio.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_IMGTECH_PISTACHIO_GPIO_H__
-#define __SOC_IMGTECH_PISTACHIO_GPIO_H__
-
-typedef unsigned int gpio_t;
-
-#endif // __SOC_IMGTECH_PISTACHIO_GPIO_H__
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
deleted file mode 100644
index cd81093fab..0000000000
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-/* SRAM memory is mapped in two different locations. Define regions in both for
- * full overlap checking and use this to guarantee they're kept in sync. */
-#define ASSERT_MIRRORED(r1, r2) \
-	_ = ASSERT((_e##r1 - _##r1) == (_e##r2 - _##r2) && \
-		   (_##r1 & 0x7fffffff) == (_##r2 & 0x7fffffff), \
-		   STR(r1 and r2 do not match!));
-
-SECTIONS
-{
-	/*
-	 * All of DRAM (other than the DMA coherent area) is accessed through
-	 * the identity mapping.
-	 */
-	DRAM_START(0x00000000)
-	/* DMA coherent area: accessed via KSEG1. */
-	DMA_COHERENT(0x00100000, 1M)
-	POSTRAM_CBFS_CACHE(0x00200000, 512K)
-	RAMSTAGE(0x00280000, 128K)
-
-	/* 0x18100000 -> 0x18540000 */
-	SOC_REGISTERS(0x18100000, 0x440000)
-	/*
-	 * GRAM becomes the SRAM.  Accessed through KSEG0 in the bootblock
-	 * and then through the identity mapping in ROM stage.
-	 */
-	SRAM_START(0x1a000000)
-	REGION(gram_bootblock, 0x1a000000, 28K, 1)
-	ROMSTAGE(0x1a007000, 60K)
-	VBOOT2_WORK(0x1a016000, 12K)
-	VBOOT2_TPM_LOG(0x1a019000, 2K)
-	PRERAM_CBFS_CACHE(0x1a019800, 46K)
-	SRAM_END(0x1a066000)
-
-	/* Bootblock executes out of KSEG0 and sets up the identity mapping.
-	 * This is identical to SRAM above, and thus also limited 64K and
-	 * needs to avoid conflicts with items set up above.
-	 */
-	BOOTBLOCK(0x9a000000, 28K)
-	REGION(kseg0_romstage, 0x9a007000, 60K, 1)
-
-	/*
-	 * Let's use SRAM for stack and CBMEM console.  Always accessed
-	 * through KSEG0.
-	 */
-	STACK(0x9b000000, 8K)
-	PRERAM_CBMEM_CONSOLE(0x9b002000, 8K)
-
-}
-
-ASSERT_MIRRORED(bootblock, gram_bootblock)
-ASSERT_MIRRORED(romstage, kseg0_romstage)
diff --git a/src/soc/imgtec/pistachio/include/soc/spi.h b/src/soc/imgtec/pistachio/include/soc/spi.h
deleted file mode 100644
index f23cca5821..0000000000
--- a/src/soc/imgtec/pistachio/include/soc/spi.h
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Imagination Technologies
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#ifndef __SOC_IMGTEC_DANUBE_SPI_H__
-#define __SOC_IMGTEC_DANUBE_SPI_H__
-
-#include <arch/types.h>
-
-#define spi_read_reg_field(regval, field)		\
-(							\
-	((field##_MASK) == 0xFFFFFFFF) ?		\
-	(regval) :					\
-	(((regval) & (field##_MASK)) >> (field##_SHIFT))\
-)
-
-#define spi_write_reg_field(regval, field, val)		\
-(							\
-	((field##_MASK) == 0xFFFFFFFF) ?		\
-	(val) :						\
-	(((regval) & ~(field##_MASK)) |			\
-	(((val) << (field##_SHIFT)) & (field##_MASK)))	\
-)
-
-/*
- * Parameter register
- * Each of these corresponds to a single port (ie CS line) in the interface
- * Fields	Name		Description
- * ======	====		===========
- * b31:24	CLK_RATE	Bit Clock rate = (24.576 * value / 512) MHz
- * b23:16	CS_SETUP	Chip Select setup = (40 * value) ns
- * b15:8	CS_HOLD		Chip Select hold = (40 * value) ns
- * b7:0		CS_DELAY	Chip Select delay = (40 * value) ns
- */
-
-#define SPIM_CLK_DIVIDE_MASK     (0xFF000000)
-#define SPIM_CS_SETUP_MASK       (0x00FF0000)
-#define SPIM_CS_HOLD_MASK        (0x0000FF00)
-#define SPIM_CS_DELAY_MASK       (0x000000FF)
-#define SPIM_CS_PARAM_MASK      (SPIM_CS_SETUP_MASK \
-				| SPIM_CS_HOLD_MASK \
-				| SPIM_CS_DELAY_MASK)
-
-#define SPIM_CLK_DIVIDE_SHIFT            (24)
-#define SPIM_CS_SETUP_SHIFT              (16)
-#define SPIM_CS_HOLD_SHIFT                (8)
-#define SPIM_CS_DELAY_SHIFT               (0)
-#define SPIM_CS_PARAM_SHIFT               (0)
-
-/* Control register */
-
-#define SPFI_DRIBBLE_COUNT_MASK  (0x000e0000)
-#define SPFI_MEMORY_IF_MASK      (0x00008000)
-#define SPIM_BYTE_DELAY_MASK     (0x00004000)
-#define SPIM_CS_DEASSERT_MASK    (0x00002000)
-#define SPIM_CONTINUE_MASK       (0x00001000)
-#define SPIM_SOFT_RESET_MASK     (0x00000800)
-#define SPIM_SEND_DMA_MASK       (0x00000400)
-#define SPIM_GET_DMA_MASK        (0x00000200)
-#define SPIM_EDGE_TX_RX_MASK     (0x00000100)
-#define SPFI_TRNSFR_MODE_MASK    (0x000000e0)
-#define SPFI_TRNSFR_MODE_DQ_MASK (0x0000001c)
-#define SPFI_TX_RX_MASK          (0x00000002)
-#define SPFI_EN_MASK             (0x00000001)
-
-#define SPFI_DRIBBLE_COUNT_SHIFT         (17)
-#define SPFI_MEMORY_IF_SHIFT             (15)
-#define SPIM_BYTE_DELAY_SHIFT            (14)
-#define SPIM_CS_DEASSERT_SHIFT           (13)
-#define SPIM_CONTINUE_SHIFT              (12)
-#define SPIM_SOFT_RESET_SHIFT            (11)
-#define SPIM_SEND_DMA_SHIFT              (10)
-#define   SPIM_GET_DMA_SHIFT              (9)
-#define SPIM_EDGE_TX_RX_SHIFT             (8)
-#define SPFI_TRNSFR_MODE_SHIFT            (5)
-#define SPFI_TRNSFR_MODE_DQ_SHIFT         (2)
-#define SPFI_TX_RX_SHIFT                  (1)
-#define SPFI_EN_SHIFT                     (0)
-
-/* Transaction register */
-
-#define SPFI_TSIZE_MASK           (0xffff0000)
-#define SPFI_CMD_LENGTH_MASK      (0x0000e000)
-#define SPFI_ADDR_LENGTH_MASK     (0x00001c00)
-#define SPFI_DUMMY_LENGTH_MASK    (0x000003e0)
-#define SPFI_PI_LENGTH_MASK       (0x0000001c)
-
-#define SPFI_TSIZE_SHIFT                  (16)
-#define SPFI_CMD_LENGTH_SHIFT             (13)
-#define SPFI_ADDR_LENGTH_SHIFT            (10)
-#define SPFI_DUMMY_LENGTH_SHIFT            (5)
-#define SPFI_PI_LENGTH_SHIFT               (2)
-
-/* Port state register */
-
-#define SPFI_PORT_SELECT_MASK    (0x00700000)
-/* WARNING the following bits are reversed */
-#define SPFI_CLOCK0_IDLE_MASK    (0x000f8000)
-#define SPFI_CLOCK0_PHASE_MASK   (0x00007c00)
-#define SPFI_CS0_IDLE_MASK       (0x000003e0)
-#define SPFI_DATA0_IDLE_MASK     (0x0000001f)
-
-#define SPIM_CLOCK0_IDLE_MASK    (0x000f8000)
-#define SPIM_CLOCK0_PHASE_MASK   (0x00007c00)
-#define SPIM_CS0_IDLE_MASK       (0x000003e0)
-#define SPIM_DATA0_IDLE_MASK     (0x0000001f)
-
-#define SPIM_PORT0_MASK          (0x00084210)
-
-#define SPFI_PORT_SELECT_SHIFT           (20)
-/* WARNING the following bits are reversed, bit 0 is highest */
-#define SPFI_CLOCK0_IDLE_SHIFT           (19)
-#define SPFI_CLOCK0_PHASE_SHIFT          (14)
-#define SPFI_CS0_IDLE_SHIFT               (9)
-#define SPFI_DATA0_IDLE_SHIFT             (4)
-
-#define SPIM_CLOCK0_IDLE_SHIFT           (19)
-#define SPIM_CLOCK0_PHASE_SHIFT          (14)
-#define SPIM_CS0_IDLE_SHIFT               (9)
-#define SPIM_DATA0_IDLE_SHIFT             (4)
-
-
-/*
- * Interrupt registers
- * SPFI_GDOF_MASK means Rx buffer full, not an overflow, because clock stalls
- * SPFI_SDUF_MASK means Tx buffer empty, not an underflow, because clock stalls
- */
-#define SPFI_IACCESS_MASK        (0x00001000)
-#define SPFI_GDEX8BIT_MASK       (0x00000800)
-#define SPFI_ALLDONE_MASK        (0x00000200)
-#define SPFI_GDFUL_MASK          (0x00000100)
-#define SPFI_GDHF_MASK           (0x00000080)
-#define SPFI_GDEX32BIT_MASK      (0x00000040)
-#define SPFI_GDTRIG_MASK         (0x00000020)
-#define SPFI_SDFUL_MASK          (0x00000008)
-#define SPFI_SDHF_MASK           (0x00000004)
-#define SPFI_SDE_MASK            (0x00000002)
-#define SPFI_SDTRIG_MASK         (0x00000001)
-
-#define SPFI_IACCESS_SHIFT               (12)
-#define SPFI_GDEX8BIT_SHIFT              (11)
-#define SPFI_ALLDONE_SHIFT                (9)
-#define SPFI_GDFUL_SHIFT                  (8)
-#define SPFI_GDHF_SHIFT                   (7)
-#define SPFI_GDEX32BIT_SHIFT              (6)
-#define SPFI_GDTRIG_SHIFT                 (5)
-#define SPFI_SDFUL_SHIFT                  (3)
-#define SPFI_SDHF_SHIFT                   (2)
-#define SPFI_SDE_SHIFT                    (1)
-#define SPFI_SDTRIG_SHIFT                 (0)
-
-
-/* SPFI register block */
-
-#define SPFI_PORT_0_PARAM_REG_OFFSET             (0x00)
-#define SPFI_PORT_1_PARAM_REG_OFFSET             (0x04)
-#define SPFI_PORT_2_PARAM_REG_OFFSET             (0x08)
-#define SPFI_PORT_3_PARAM_REG_OFFSET             (0x0C)
-#define SPFI_PORT_4_PARAM_REG_OFFSET             (0x10)
-#define SPFI_CONTROL_REG_OFFSET                  (0x14)
-#define SPFI_TRANSACTION_REG_OFFSET              (0x18)
-#define SPFI_PORT_STATE_REG_OFFSET               (0x1C)
-
-#define SPFI_SEND_LONG_REG_OFFSET                (0x20)
-#define SPFI_SEND_BYTE_REG_OFFSET                (0x24)
-#define SPFI_GET_LONG_REG_OFFSET                 (0x28)
-#define SPFI_GET_BYTE_REG_OFFSET                 (0x2C)
-
-#define SPFI_INT_STATUS_REG_OFFSET               (0x30)
-#define SPFI_INT_ENABLE_REG_OFFSET               (0x34)
-#define SPFI_INT_CLEAR_REG_OFFSET                (0x38)
-
-#define SPFI_IMMEDIATE_STATUS_REG_OFFSET         (0x3c)
-
-#define SPFI_FLASH_BASE_ADDRESS_REG_OFFSET       (0x48)
-#define SPFI_FLASH_STATUS_REG_OFFSET             (0x4C)
-
-#define IMG_FALSE				0
-#define IMG_TRUE				1
-
-/* Number of SPIM interfaces*/
-#define SPIM_NUM_BLOCKS				2
-/* Number of chip select lines supported by the SPI master port. */
-#define SPIM_NUM_PORTS_PER_BLOCK		(SPIM_DUMMY_CS)
-/* Maximum transfer size (in bytes) for the SPI master port. */
-#define SPIM_MAX_TRANSFER_BYTES			(0xFFFF)
-/* Maximum size of a flash command: command bytes+address_bytes. */
-#define SPIM_MAX_FLASH_COMMAND_BYTES		(0x8)
-/* Write operation to fifo done in blocks of 16 words (64 bytes) */
-#define SPIM_MAX_BLOCK_BYTES			(0x40)
-/* Number of tries until timeout error is returned*/
-#define SPI_TIMEOUT_VALUE_US			500000
-
-/* SPIM initialisation function return value.*/
-enum spim_return {
-	/* Initialisation parameters are valid. */
-	SPIM_OK = 0,
-	/* Mode parameter is invalid. */
-	SPIM_INVALID_SPI_MODE,
-	/* Chip select idle level is invalid. */
-	SPIM_INVALID_CS_IDLE_LEVEL,
-	/* Data idle level is invalid. */
-	SPIM_INVALID_DATA_IDLE_LEVEL,
-	/* Chip select line parameter is invalid. */
-	SPIM_INVALID_CS_LINE,
-	/* Transfer size parameter is invalid. */
-	SPIM_INVALID_SIZE,
-	/* Read/write parameter is invalid. */
-	SPIM_INVALID_READ_WRITE,
-	/* Continue parameter is invalid. */
-	SPIM_INVALID_CONTINUE,
-	/* Invalid block index */
-	SPIM_INVALID_BLOCK_INDEX,
-	/* Extended error values */
-	/* Invalid bit rate */
-	SPIM_INVALID_BIT_RATE,
-	/* Invalid CS hold value */
-	SPIM_INVALID_CS_HOLD_VALUE,
-	/* API function called before API is initialised */
-	SPIM_API_NOT_INITIALISED,
-	/* SPI driver initialisation failed */
-	SPIM_DRIVER_INIT_ERROR,
-	/* Invalid transfer description */
-	SPIM_INVALID_TRANSFER_DESC,
-	/* Timeout */
-	SPIM_TIMEOUT
-
-};
-
-/* This type defines the SPI Mode.*/
-enum spim_mode {
-	/* Mode 0 (clock idle low, data valid on first clock transition). */
-	SPIM_MODE_0 = 0,
-	/* Mode 1 (clock idle low, data valid on second clock transition). */
-	SPIM_MODE_1,
-	/* Mode 2 (clock idle high, data valid on first clock transition). */
-	SPIM_MODE_2,
-	/* Mode 3 (clock idle high, data valid on second clock transition). */
-	SPIM_MODE_3
-
-};
-
-/* This type defines the SPIM device numbers (chip select lines). */
-enum spim_device {
-	/* Device 0 (CS0). */
-	SPIM_DEVICE0 = 0,
-	/* Device 1 (CS1). */
-	SPIM_DEVICE1,
-	/* Device 2 (CS2). */
-	SPIM_DEVICE2,
-	/* Device 3 (CS3). */
-	SPIM_DEVICE3,
-	/* Device 4 (CS4). */
-	SPIM_DEVICE4,
-	/* Dummy chip select. */
-	SPIM_DUMMY_CS
-
-};
-
-/* This structure defines communication parameters for a slave device */
-struct spim_device_parameters {
-	/* Bit rate value.*/
-	unsigned char bitrate;
-	/*
-	 * Chip select set up time.
-	 * Time taken between chip select going active and activity occurring
-	 * on the clock, calculated by dividing the desired set up time in ns
-	 * by the Input clock period. (setup time / Input clock freq)
-	 */
-	unsigned char cs_setup;
-	/*
-	 * Chip select hold time.
-	 * Time after the last clock pulse before chip select goes inactive,
-	 * calculated by dividing the desired hold time in ns by the
-	 * Input clock period (hold time / Input clock freq).
-	 */
-	unsigned char cs_hold;
-	/*
-	 * Chip select delay time (CS minimum inactive time).
-	 * Minimum time after chip select goes inactive before chip select
-	 * can go active again, calculated by dividing the desired delay time
-	 * in ns by the Input clock period (delay time / Input clock freq).
-	 */
-	unsigned char cs_delay;
-	/* SPI Mode. */
-	enum spim_mode spi_mode;
-	/* Chip select idle level (0=low, 1=high, Others=invalid). */
-	unsigned int cs_idle_level;
-	/* Data idle level (0=low, 1=high, Others=invalid). */
-	unsigned int data_idle_level;
-
-};
-
-/* Command transfer mode */
-enum command_mode {
-	/* Command, address, dummy and PI cycles are transferred on sio0 */
-	SPIM_CMD_MODE_0 = 0,
-	/*
-	 * Command and Address are transferred on sio0 port only but dummy
-	 * cycles and PI is transferred on all the interface ports.
-	 */
-	SPIM_CMD_MODE_1,
-	/*
-	 * Command is transferred on sio0 port only but address, dummy
-	 * and PI is transferred on all the interface portS
-	 */
-	SPIM_CMD_MODE_2,
-	/*
-	 * Command, address, dummy and PI bytes are transferred on all
-	 * the interfaces
-	 */
-	SPIM_CMD_MODE_3
-};
-
-/* Data transfer mode */
-enum transfer_mode {
-	/* Transfer data in single mode */
-	SPIM_DMODE_SINGLE = 0,
-	/* Transfer data in dual mode */
-	SPIM_DMODE_DUAL,
-	/* Transfer data in quad mode */
-	SPIM_DMODE_QUAD
-};
-
-/* This structure contains parameters that describe an SPIM operation. */
-struct spim_buffer {
-	/* The buffer to read from or write to. */
-	unsigned char *buffer;
-
-	/* Number of bytes to read/write. Valid range is 0 to 65536 bytes. */
-	unsigned int size;
-
-	/* Read/write select. TRUE for read, FALSE for write, Others-invalid.*/
-	int isread;
-
-	/*
-	 * ByteDelay select.
-	 * Selects whether or not a delay is inserted between bytes.
-	 * 0 - Minimum inter-byte delay
-	 * 1 - Inter-byte delay of (cs_hold/master_clk half period)*master_clk.
-	 */
-	int inter_byte_delay;
-};
-
-#endif /* __SOC_IMGTEC_DANUBE_SPI_H__ */