diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2014-11-05 17:50:09 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-09 00:29:09 +0200 |
| commit | 52a887985300cf11fbc183f6a4a4408ff9a45ec6 (patch) | |
| tree | 10cef88314046050b41057689d1e0a8e7b7cefb0 /src/soc/imgtec/pistachio/include | |
| parent | 771819a3806b5e60e3db73b2779072ee0f23890f (diff) | |
pistachio: implement timer support
C0_COUNT register is a free running counter clocked by the CPU
frequency divided by two. On the FPGA board it results in 25 MHz, on
real SOCs it will have to be figured out later.
Some magic addresses and numbers are used to find out if the code is
running on the FPGA board.
timestamp_get() and timer_monotonic_get() are kept in the same file.
The CPU initialization makes sure that CO COUNT is in fact enabled and
starts from zero.
BRANCH=none
BUG=chrome-os-partner:33595,chrome-os-partner:31438
TEST=with timer enabled, the startup code properly initializes UART
and prints the coreboot bootblock banner message on the serial
console.
Change-Id: I98fe330b961f677448b222917ab7d586494ed4b7
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: a7324221c1d856ac72fa2b0ab586b5ea8cab3a05
Original-Change-Id: I2d518213de939e91a35f8aea174aed76d297dd72
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227888
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9188
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/imgtec/pistachio/include')
| -rw-r--r-- | src/soc/imgtec/pistachio/include/soc/cpu.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/cpu.h b/src/soc/imgtec/pistachio/include/soc/cpu.h index c61c58dfca..72775b5cbe 100644 --- a/src/soc/imgtec/pistachio/include/soc/cpu.h +++ b/src/soc/imgtec/pistachio/include/soc/cpu.h @@ -21,4 +21,11 @@ #define IMG_SPIM0_BASE_ADDRESS 0xB8100F00 #define IMG_SPIM1_BASE_ADDRESS 0xB8101000 +/* + * Reading at this address allows to identify the platform the code is running + * on. + */ +#define IMG_PLATFORM_ID() (*((unsigned *)0xB8149060)) +#define IMG_PLATFORM_ID_SILICON 0xF00D0006 + #endif |