diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2023-04-24 15:50:15 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2023-07-13 01:04:37 +0000 |
| commit | 433343eaaa987432242909fe4b1b482d53b66b4a (patch) | |
| tree | d9c027444040d35cef6a1ad7d27a38b74fd53b1c /src/soc/example/min86/chip.c | |
| parent | 0cc560fd3cde1cef2fbe0946668633c1136bfa9f (diff) | |
soc/intel/alderlake: Hook up UPD LowerBasicMemTestSize
Hook the newly exposed LowerBasicMemTestSize UPD up so that
boards can configure is via devicetree.
BUG=b:268546941
TEST=Verified by enabling/disabling the UPD on google/brya
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib813e9f3b7419a3cb54b4e176dcc5cc74a783dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74718
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Diffstat (limited to 'src/soc/example/min86/chip.c')
0 files changed, 0 insertions, 0 deletions