diff options
| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-05-03 16:26:05 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-05-05 20:06:33 +0200 |
| commit | 5caf89b9f848bbab199e7e6bd37897f6464e4d23 (patch) | |
| tree | eea935f4cff74566f531bf9d6f0c6b21a3885f81 /src/soc/dmp/vortex86ex/southbridge.h | |
| parent | f7dd6d5da13131d5161185c60e757ae4c4406f46 (diff) | |
dmp/vortex86ex: Merge northbridge and southbridge into soc
Change-Id: I16c04452d2d6c3205aea29fe8aa8fad8fc485a46
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14600
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/dmp/vortex86ex/southbridge.h')
| -rw-r--r-- | src/soc/dmp/vortex86ex/southbridge.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/soc/dmp/vortex86ex/southbridge.h b/src/soc/dmp/vortex86ex/southbridge.h new file mode 100644 index 0000000000..c2b91027ae --- /dev/null +++ b/src/soc/dmp/vortex86ex/southbridge.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_H +#define SOUTHBRIDGE_H + +#define SB PCI_DEV(0, 7, 0) +#define SB_REG_LPCCR 0x41 +#define SB_REG_FRCSCR 0x42 +#define SB_REG_PIRQ_ROUTE 0x58 +#define SB_REG_UART_CFG_IO_BASE 0x60 +#define SB_REG_GPIO_CFG_IO_BASE 0x62 +#define SB_REG_CS_BASE0 0x90 +#define SB_REG_CS_BASE_MASK0 0x94 +#define SB_REG_CS_BASE1 0x98 +#define SB_REG_CS_BASE_MASK1 0x9c +#define SB_REG_IPPCR 0xb0 +#define SB_REG_EXT_PIRQ_ROUTE 0xb4 +#define SB_REG_OCDCR 0xbc +#define SB_REG_IPFCR 0xc0 +#define SB_REG_FRWPR 0xc4 +#define SB_REG_STRAP 0xce +#define SB_REG_II2CCR 0xd4 + +#define SB1 PCI_DEV(0, 7, 1) +#define SB1_REG_EXT_PIRQ_ROUTE2 0xb4 + +#define SYSTEM_CTL_PORT 0x92 + +#endif /* SOUTHBRIDGE_H */ |