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| author | Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> | 2020-09-02 12:13:35 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-09-03 21:42:39 +0000 |
| commit | ae437c575f7b53a579230b16632f331f9e8edc30 (patch) | |
| tree | d873cf0ec5f3ef88ae50fcd994485328df6adc1d /src/soc/cavium/common/include | |
| parent | b132bf5a87784a8a57677f43607095330be9f3a1 (diff) | |
soc/amd/picasso/acpi: Remove padding in IVRS table caused by realignment.
Previous CL (1916f8969b10e27fe06b3e0eb1caae632bd947f6) misinterpreted
spec as requiring size alignment on all IVHD device entries. The correct
requirement specifies only for 4-byte entries. The unneeded realignments
result in gaps in the table. The kernel hangs in early boot due to the
malformed table.
Remove 8-byte entry alignment.
BUG=b:166519072
TEST=Boot fully to morphius board with and without amd_iommu kernel
parameter. Confirm IVRS contains no alignment gaps/corruption.
Change-Id: Iddcff98279be1d910936b13391dd2448a3bb2d74
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/cavium/common/include')
0 files changed, 0 insertions, 0 deletions