diff options
author | David Hendricks <dhendricks@fb.com> | 2017-12-01 20:49:48 -0800 |
---|---|---|
committer | Patrick Rudolph <siro@das-labor.org> | 2018-07-10 07:01:57 +0000 |
commit | 8cbd569f74d8929387730e45b0d6e993b1365c02 (patch) | |
tree | ca6414a4d81e37280887b0da0f1a6120a50f0a3a /src/soc/cavium/common/Makefile.inc | |
parent | 03d31427338ba59d3a354ac1beb3b0c153471768 (diff) |
cavium: Add CN81xx SoC and eval board support
This adds Cavium CN81xx SoC and SFF EVB files.
Code is based off of Cavium's Octeon-TX SDK:
https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK
BDK coreboot differences:
bootblock:
- Get rid of BDK header
- Add Kconfig for link address
- Move CAR setup code into assembly
- Move unaligned memory access enable into assembly
- Implement custom bootblock entry function
- Add CLIB and CSIB blobs
romstage:
- Use minimal DRAM init only
devicetree:
- Convert FTD to static C file containing key value pairs
Tested on CN81xx:
- Boots to payload
- Tested with GNU/Linux 4.16.3
- All hardware is usable (after applying additional commits)
Implemented in future commits:
- Vboot integration
- MMU suuport
- L2 Cache handling
- ATF from external repo
- Devicetree patching
- Extended DRAM testing
- UART init
Not working:
- Booting a payload
- Booting upstream ATF
TODO:
- Configuration straps
Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688
Signed-off-by: David Hendricks <dhendricks@fb.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/23037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc/cavium/common/Makefile.inc')
-rw-r--r-- | src/soc/cavium/common/Makefile.inc | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/src/soc/cavium/common/Makefile.inc b/src/soc/cavium/common/Makefile.inc new file mode 100644 index 0000000000..89add5f3f1 --- /dev/null +++ b/src/soc/cavium/common/Makefile.inc @@ -0,0 +1,58 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2017-present Facebook, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_SOC_CAVIUM_COMMON),y) + +CFLAGS_arm64 += -Wstack-usage=8192 + +bootblock-$(CONFIG_BOOTBLOCK_CUSTOM) += bootblock.c + +################################################################################ +# romstage + +romstage-y += cbmem.c +romstage-y += bdk-coreboot.c + +################################################################################ +# ramstage + +ramstage-y += cbmem.c +ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c + +CPPFLAGS_common += -Isrc/soc/cavium/common/include + +ROM_HEADER_BIN := $(objgenerated)/rom_header.bin +ROM_HEADER_SOURCES += rom_clib_s_nbl1fw +ROM_HEADER_SOURCES += rom_csib_s_nbl1fw + +ROM_HEADER_DEPS := $(foreach f, $(ROM_HEADER_SOURCES), src/soc/cavium/common/$(f).bin.hex) + +# Include ROM header +$(ROM_HEADER_BIN): $(ROM_HEADER_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(ROM_HEADER_BIN) + @printf " GEN $(subst $(obj)/,,$(@))\n" + dd if=/dev/zero ibs=1 count=$$(($(shell stat --printf="%s" $(objcbfs)/bootblock.raw.bin) + 0x10000)) of=$@ status=none + # Insert CLIB at 0x0 and CSIB at 0x100 + dd if=$(ROM_HEADER_BIN) of=$@ bs=1 seek=0 conv=notrunc status=none + # Insert bootblock at 0x10000 + dd if=$(objcbfs)/bootblock.raw.bin of=$@ bs=1 seek=$$((0x10000)) conv=notrunc status=none + +endif |