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authorAnil Kumar <anil.kumar.k@intel.com>2022-02-01 12:59:03 -0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-02-04 16:52:28 +0000
commitc6b65c1a811e25dc909659ff4890eb76e16dba8a (patch)
treed1ee55c15e476343083a6f62437569d185e108a2 /src/soc/cavium/cn81xx/include/atf
parentb6cf642732f59e732c21dffb98bdd91a33324022 (diff)
soc/intel/alderlake: Enable USB2 port reset message on Type-C ports
This change is added to address the issue of USB3 ports downgrading to high speed during low power modes and not returning back to super speed. The patch enables port reset event on USB2 ports. This event is is passed to USB3 upstream ports to upgrade back to super speed (USB3) after a downgrade during low power state BUG=b:193287279 TEST=Built coreboot on Gimble and tested type A pen drive detects as super speed device Change-Id: Iabc6f308992bf3868da66f152c6d7b0164e64bea Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/cavium/cn81xx/include/atf')
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