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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2020-11-11 12:44:28 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-11-20 08:36:26 +0000 |
| commit | 0fd62f5b7963b2128d48aca190a93e9b94d70d13 (patch) | |
| tree | aee43348240807a27a6d521cb9febe22f24fc641 /src/soc/cavium/cn81xx/bootblock_custom.S | |
| parent | 957a36397ad7edc004f1f432a26ed43f86480bbf (diff) | |
vc/google/chromeos/sar: Make "SAR not found" log a debug message
coreboot might not store wifi SAR values in VPD and may store it in
CBFS. Logging the message with 'error' severity may interfere
with automated test tool.
Lowering severity to BIOS_DEBUG avoids this issue.
BUG=b:171931401
BRANCH=None
TEST=Severity of message is reduced and we don't see it as an error
Change-Id: I5c122a57cfe92b27e0291933618ca13d8e1889ba
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/cavium/cn81xx/bootblock_custom.S')
0 files changed, 0 insertions, 0 deletions