soc/broadcom/cygnus: Update DDR Kconfig

The DDR speed Kconfig symbols needed to either be added to the Kconfig
tree, or have the code associated with them removed.  I chose to add
the symbols.

- Add symbols for DDR333 - DDR667 to cygnus Kconfig.  These should be
selected by the mainboard.
- Rename symbols from DDRXXX to CYGNUS_DDRXXX to match the existing
CYGNUS_DDR800 symbol.
- Rename the non Kconfig #define CONFIG_DRAM_FREQ to CYGNUS_DRAM_FREQ
because having other #defines look like Kconfig symbols is confusing.
- Change #ifdef CONFIG_DDRXXX to use IS_ENABLED

Change-Id: I3f5957a595072434c21af0002d57ac49b48b1e43
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17386
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>

3 files changed, 33 insertions, 22 deletions

diff --git a/src/soc/broadcom/cygnus/Kconfig b/src/soc/broadcom/cygnus/Kconfig
index d4c34c9243..46109030ce 100644
--- a/src/soc/broadcom/cygnus/Kconfig
+++ b/src/soc/broadcom/cygnus/Kconfig
@@ -37,6 +37,18 @@ config CONSOLE_SERIAL_UART_ADDRESS
 	depends on DRIVERS_UART
 	default 0x18023000
 
+config CYGNUS_DDR333
+	def_bool n
+
+config CYGNUS_DDR400
+	def_bool n
+
+config CYGNUS_DDR533
+	def_bool n
+
+config CYGNUS_DDR667
+	def_bool n
+
 config CYGNUS_DDR800
 	bool "DDR Speed at 800MHz"
 	default y
diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c
index bc39b2ae33..b6bbf4a86f 100644
--- a/src/soc/broadcom/cygnus/ddr_init.c
+++ b/src/soc/broadcom/cygnus/ddr_init.c
@@ -29,24 +29,24 @@ extern unsigned int ddr2_init_tab_1066[];
 extern unsigned int ddr2_mode_reg_tab[];
 #endif
 
-#ifdef CONFIG_DDR333
-#define CONFIG_DRAM_FREQ 333
+#if IS_ENABLED(CONFIG_CYGNUS_DDR333)
+#define CYGNUS_DRAM_FREQ 333
 extern unsigned int ddr3_init_tab_667[];
 #endif
-#ifdef CONFIG_DDR400
-#define CONFIG_DRAM_FREQ 400
+#if IS_ENABLED(CONFIG_CYGNUS_DDR400)
+#define CYGNUS_DRAM_FREQ 400
 extern unsigned int ddr3_init_tab_800[];
 #endif
-#ifdef CONFIG_DDR533
-#define CONFIG_DRAM_FREQ 533
+#if IS_ENABLED(CONFIG_CYGNUS_DDR533)
+#define CYGNUS_DRAM_FREQ 533
 extern unsigned int ddr3_init_tab_1066[];
 #endif
-#ifdef CONFIG_DDR667
-#define CONFIG_DRAM_FREQ 667
+#if IS_ENABLED(CONFIG_CYGNUS_DDR667)
+#define CYGNUS_DRAM_FREQ 667
 extern unsigned int ddr3_init_tab_1333[];
 #endif
 #if IS_ENABLED(CONFIG_CYGNUS_DDR800)
-#define CONFIG_DRAM_FREQ 800
+#define CYGNUS_DRAM_FREQ 800
 extern unsigned int ddr3_init_tab_1600[];
 #endif
 
@@ -485,10 +485,10 @@ int is_ddr_32bit(void)
 
 static uint32_t get_ddr_clock(uint32_t sku_id, int ddr_type)
 {
-#ifdef CONFIG_DRAM_FREQ
-	return  CONFIG_DRAM_FREQ;
+#ifdef CYGNUS_DRAM_FREQ
+	return  CYGNUS_DRAM_FREQ;
 #else
-	#error Please set DDR frequency (CONFIG_DRAM_FREQ must be set)
+	#error Please set DDR frequency (CYGNUS_DRAM_FREQ must be set)
 #endif
 }
 
@@ -1461,28 +1461,27 @@ void ddr_init2(void)
 	if (ddr_type) {
 		/* DDR3 */
 		switch(ddr_clk) {
-#ifdef CONFIG_DDR333
+#if IS_ENABLED(CONFIG_CYGNUS_DDR333)
 			case 333:
 				ddr_init_regs(ddr3_init_tab_667);
 				break;
 #endif
-#ifdef CONFIG_DDR400
+#if IS_ENABLED(CONFIG_CYGNUS_DDR400)
 			case 400:
 				ddr_init_regs(ddr3_init_tab_800);
 				break;
 #endif
-#ifdef CONFIG_DDR533
+#if IS_ENABLED(CONFIG_CYGNUS_DDR533)
 			case 533:
 				ddr_init_regs(ddr3_init_tab_1066);
 				break;
 #endif
-#ifdef CONFIG_DDR667
+#if IS_ENABLED(CONFIG_CYGNUS_DDR667)
 			case 667:
 				ddr_init_regs(ddr3_init_tab_1333);
 				break;
 #endif
-#if (defined(CONFIG_DDR750) || IS_ENABLED(CONFIG_CYGNUS_DDR800))
-			case 750:
+#if IS_ENABLED(CONFIG_CYGNUS_DDR800)
 			case 800:
 				ddr_init_regs(ddr3_init_tab_1600);
 				break;
diff --git a/src/soc/broadcom/cygnus/ddr_init_table.c b/src/soc/broadcom/cygnus/ddr_init_table.c
index 7c8a89f3bc..20eb5e6550 100644
--- a/src/soc/broadcom/cygnus/ddr_init_table.c
+++ b/src/soc/broadcom/cygnus/ddr_init_table.c
@@ -292,7 +292,7 @@ const unsigned int ddr2_init_tab_400[] = {
 };
 #endif
 
-#ifdef CONFIG_DDR333
+#if IS_ENABLED(CONFIG_CYGNUS_DDR333)
 const unsigned int ddr3_init_tab_667[] = {
         0, 0x00000600,
         1, 0x00000000,
@@ -552,7 +552,7 @@ const unsigned int ddr3_init_tab_667[] = {
 };
 #endif
 
-#ifdef CONFIG_DDR400
+#if IS_ENABLED(CONFIG_CYGNUS_DDR400)
 const unsigned int ddr3_init_tab_800[] = {
         14, 0x01000000,
         36, 0x0a140a0a,
@@ -864,7 +864,7 @@ const unsigned int ddr3_init_tab_800[] = {
 };
 #endif
 
-#ifdef CONFIG_DDR533
+#if IS_ENABLED(CONFIG_CYGNUS_DDR533)
 const unsigned int ddr3_init_tab_1066[] = {
         14, 0x01000000,
         36, 0x0a140a0a,
@@ -1176,7 +1176,7 @@ const unsigned int ddr3_init_tab_1066[] = {
 };
 #endif
 
-#ifdef CONFIG_DDR667
+#if IS_ENABLED(CONFIG_CYGNUS_DDR667)
 const unsigned int ddr3_init_tab_1333[] = {
         14, 0x01000000,
         36, 0x0a140a0a,