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| author | Nico Huber <nico.huber@secunet.com> | 2017-03-30 17:47:24 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-06-06 17:27:10 +0200 |
| commit | da94e171b57c77217b5bd8ad071208475f33cf56 (patch) | |
| tree | 4fbd98143ecba743fc9d3cbd8fc45c646d3dcf46 /src/soc/broadcom/cygnus/soc.c | |
| parent | 0660c6c1ffb8ff1de04d62432a22b2f0a625fca2 (diff) | |
inteltool/ahci: Add Skylake support
The SATA device moved from 0:1f.2 to 0:17.0, 0:1f.2 became PMC. We
detect that by checking the PCI device class.
The ABAR MMIO space has grown to 2KiB and up to 8 ports are supported
now. For backwards compatibility, only dump port registers of ports
that are enabled in the Ports Implemented (PI) register.
Change-Id: I8e0f07d7359d92f689882b5afefa5ffb3766ee8b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/broadcom/cygnus/soc.c')
0 files changed, 0 insertions, 0 deletions