diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-02 19:45:21 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-07 16:53:39 +0000 |
| commit | f0c1c9791b2909e5d963d55b215485f66f1fc62e (patch) | |
| tree | 9ec89e8a4392f9f83c31499301b17c5d72583815 /src/soc/amd | |
| parent | 059370898cd7d4fdd21538c187a219ea72ad36ce (diff) | |
soc/amd/stoneyridge: request binaryPI to use \_SB_ scope in PSTATE SSDT
Instead of having binaryPI generate a PSTATE SSDT that uses \_PR_ as the
scope for the CPU objects and patching this SSDT in coreboot to use the
\_SB_ scope in patch_ssdt_processor_scope, request binaryPI to use the
\_SB_ scope instead by setting the late platform configuration option
ProcessorScopeInSb to true.
TEST=Careena still boots and Linux doesn't show any ACPI errors with
this patch applied. With only patch_ssdt_processor_scope removed, but
the ProcessorScopeInSb option not set, Linux will complain that it can't
resolve the \PR.P00x symbols.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If88820a0f5df923f129e2e3b5335f5f0e38ee7f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/pi/agesawrapper.c | 3 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 16 |
2 files changed, 3 insertions, 16 deletions
diff --git a/src/soc/amd/common/pi/agesawrapper.c b/src/soc/amd/common/pi/agesawrapper.c index 40858553df..2539a1d68a 100644 --- a/src/soc/amd/common/pi/agesawrapper.c +++ b/src/soc/amd/common/pi/agesawrapper.c @@ -266,6 +266,9 @@ static AGESA_STATUS amd_init_late(AMD_LATE_PARAMS *LateParams) LateParams->GnbLateConfiguration.FchIoapicId = FCH_IOAPIC_ID; } + /* Make binaryPI use \_SB_ as processor object scope in PSTATE SSDT */ + LateParams->PlatformConfig.ProcessorScopeInSb = true; + timestamp_add_now(TS_AGESA_INIT_LATE_START); Status = amd_dispatch(LateParams); timestamp_add_now(TS_AGESA_INIT_LATE_END); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 6389cc439c..e318024dd8 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -207,21 +207,6 @@ static void northbridge_fill_ssdt_generator(const struct device *device) acpigen_pop_len(); } -static void patch_ssdt_processor_scope(acpi_header_t *ssdt) -{ - unsigned int len = ssdt->length - sizeof(acpi_header_t); - unsigned int i; - - for (i = sizeof(acpi_header_t); i < len; i++) { - /* Search for _PR_ scope and replace it with _SB_ */ - if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) - *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; - } - /* Recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); -} - static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) @@ -296,7 +281,6 @@ static unsigned long agesa_write_acpi_tables(const struct device *device, printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); if (ssdt != NULL) { - patch_ssdt_processor_scope(ssdt); memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *)current; current += ssdt->length; |