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| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2021-03-04 18:09:44 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-03-10 20:30:20 +0000 |
| commit | e1a27f2e491b666f69fb198546370741e6125eda (patch) | |
| tree | 14e30c075c93b79665b85fa2101bf94382f1217c /src/soc/amd | |
| parent | 1add48381955fa60d4ec9fb4e1d30d62703925de (diff) | |
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02
The headers added are generated as per FSP v2081_02.
Previous FSP version was v2037.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Add DevIntConfigPtr and NumOfDevIntConfig UPDs in Fsps.h
BUG=b:180758116
BRANCH=None
TEST=Build and boot ADLRVP
Cq-Depend: chrome-internal:3669105
Change-Id: Ib99748a428709ffad27d47f600e00bd91b70d8f3
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51248
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
0 files changed, 0 insertions, 0 deletions