soc/amd/genoa: Add basic ACPI support

- DSDT
- MADT
- SSDT CPUs

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0c86694ae83e9e6aa06a50a8a35bf2b24bc8ab65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76530
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 88 insertions, 0 deletions

diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig
index 2068c44fdc..6cb4a8a174 100644
--- a/src/soc/amd/genoa/Kconfig
+++ b/src/soc/amd/genoa/Kconfig
@@ -5,13 +5,16 @@ if SOC_AMD_GENOA
 
 config SOC_SPECIFIC_OPTIONS
 	def_bool y
+	select ACPI_SOC_NVS
 	select ARCH_X86
+	select HAVE_ACPI_TABLES
 	select HAVE_EXP_X86_64_SUPPORT
 	select HAVE_SMI_HANDLER
 	select RESET_VECTOR_IN_RAM
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK_ACPI
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
+	select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
 	select SOC_AMD_COMMON_BLOCK_AOAC
 	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
 	select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
@@ -32,6 +35,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_SMM
 	select SOC_AMD_COMMON_BLOCK_SMU
 	select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY
+	select SOC_AMD_COMMON_BLOCK_SVI3
 	select SOC_AMD_COMMON_BLOCK_TSC
 	select SOC_AMD_COMMON_BLOCK_UART
 	select SOC_AMD_COMMON_BLOCK_UCODE
@@ -179,4 +183,12 @@ config HEAP_SIZE
 	hex
 	default 0x200000
 
+config ACPI_SSDT_PSD_INDEPENDENT
+	bool "Allow core p-state independent transitions"
+	default y
+	help
+	  AMD recommends the ACPI _PSD object to be configured to cause
+	  cores to transition between p-states independently. A vendor may
+	  choose to generate _PSD object to allow cores to transition together.
+
 endif # SOC_AMD_GENOA
diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc
index 4b47886872..54c4a27883 100644
--- a/src/soc/amd/genoa/Makefile.inc
+++ b/src/soc/amd/genoa/Makefile.inc
@@ -13,6 +13,7 @@ bootblock-y	+= aoac.c
 
 romstage-y	+= romstage.c
 
+ramstage-y	+= acpi.c
 ramstage-y	+= aoac.c
 ramstage-y	+= chip.c
 ramstage-y	+= cpu.c
@@ -23,6 +24,7 @@ ramstage-y	+= mca.c
 
 smm-y		+= smihandler.c
 
+CPPFLAGS_common += -I$(src)/soc/amd/genoa/acpi
 CPPFLAGS_common += -I$(src)/soc/amd/genoa/include
 
 ifeq ($(call int-gt, $(CONFIG_ROM_SIZE) 0x1000000), 1)
diff --git a/src/soc/amd/genoa/acpi.c b/src/soc/amd/genoa/acpi.c
new file mode 100644
index 0000000000..1f7b7bf02f
--- /dev/null
+++ b/src/soc/amd/genoa/acpi.c
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* ACPI - create the Fixed ACPI Description Tables (FADT) */
+
+#include <acpi/acpi.h>
+#include <amdblocks/acpi.h>
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/cpu.h>
+#include <amdblocks/data_fabric.h>
+#include <arch/ioapic.h>
+#include <console/console.h>
+#include <vendorcode/amd/opensil/genoa_poc/opensil.h>
+
+/* TODO: this can go in a common place */
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	struct device *dev = NULL;
+	while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN)) != NULL) {
+		struct resource *res = probe_resource(dev, IOMMU_IOAPIC_IDX);
+		if (!res)
+			continue;
+
+		current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current,
+						   res->base);
+	}
+
+	return current;
+}
+
+void acpi_fill_fadt(acpi_fadt_t *fadt)
+{
+	/* Fill in pm1_evt, pm1_cnt, pm_tmr, gpe0_blk from openSIL input structure */
+	opensil_fill_fadt_io_ports(fadt);
+
+	fadt->pm1_evt_len = 4;	/* 32 bits */
+	fadt->pm1_cnt_len = 2;	/* 16 bits */
+	fadt->pm_tmr_len = 4;	/* 32 bits */
+	fadt->gpe0_blk_len = 8;	/* 64 bits */
+
+	fill_fadt_extended_pm_regs(fadt);
+
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; /* legacy free default */
+	fadt->flags |=	ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */
+			ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_S4_RTC_WAKE |
+			ACPI_FADT_32BIT_TIMER |
+			ACPI_FADT_PCI_EXPRESS_WAKE |
+			ACPI_FADT_PLATFORM_CLOCK |
+			ACPI_FADT_S4_RTC_VALID |
+			ACPI_FADT_REMOTE_POWER_ON;
+
+	fadt->x_firmware_ctl_l = 0;	/* set to 0 if firmware_ctrl is used */
+	fadt->x_firmware_ctl_h = 0;
+}
+
+/* There are only the following 2 C-states reported by the reference firmware */
+const acpi_cstate_t cstate_cfg_table[] = {
+	[0] = {
+		.ctype = 1,
+		.latency = 1,
+		.power = 0,
+	},
+	[1] = {
+		.ctype = 2,
+		.latency = 0x12,
+		.power = 0,
+	},
+};
+
+const acpi_cstate_t *get_cstate_config_data(size_t *size)
+{
+	*size = ARRAY_SIZE(cstate_cfg_table);
+	return cstate_cfg_table;
+}