cpu/x86/smm: Promote smm_subregion()

No need to limit these declarations to FSP. Both
PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE
can be built on top of this.

Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

8 files changed, 6 insertions, 42 deletions

diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index bee2b4b49f..84f4729b20 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -18,6 +18,7 @@
 #include <cpu/x86/mp.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
 #include <cpu/amd/msr.h>
 #include <cpu/x86/lapic.h>
 #include <device/device.h>
diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h
index 65705b93f3..57373c9a08 100644
--- a/src/soc/amd/picasso/include/soc/northbridge.h
+++ b/src/soc/amd/picasso/include/soc/northbridge.h
@@ -99,29 +99,8 @@
 #define NB_CAPABILITIES2	0x84
 #define   CMP_CAP_MASK		0xff
 
-enum {
-	/* SMM handler area. */
-	SMM_SUBREGION_HANDLER,
-	/* SMM cache region. */
-	SMM_SUBREGION_CACHE,
-	/* Chipset specific area. */
-	SMM_SUBREGION_CHIPSET,
-	/* Total sub regions supported. */
-	SMM_SUBREGION_NUM,
-};
-
 void amd_initcpuio(void);
 
-/*
- * Fills in the arguments for the entire SMM region covered by chipset
- * protections. e.g. TSEG.
- */
-void smm_region_info(void **start, size_t *size);
-/*
- * Fills in the start and size for the requested SMM subregion. Returns
- * 0 on success, < 0 on failure.
- */
-int smm_subregion(int sub, void **start, size_t *size);
 void domain_enable_resources(struct device *dev);
 void domain_set_resources(struct device *dev);
 void fam15_finalize(void *chip_info);
diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c
index 7c855bb1e1..8eb2e39883 100644
--- a/src/soc/amd/picasso/ramtop.c
+++ b/src/soc/amd/picasso/ramtop.c
@@ -19,6 +19,7 @@
 #include <stdint.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cbmem.h>
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 950b41f5a3..458886d70c 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -19,6 +19,7 @@
 #include <arch/acpi.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <cpu/amd/mtrr.h>
 #include <cbmem.h>
 #include <commonlib/helpers.h>
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index f751dc8046..9961153b0b 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -18,6 +18,7 @@
 #include <cpu/x86/mp.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
 #include <cpu/amd/msr.h>
 #include <cpu/x86/lapic.h>
 #include <device/device.h>
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index 60a6ea22bb..a0d7ce88dd 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -99,27 +99,6 @@
 #define NB_CAPABILITIES2	0x84
 #define   CMP_CAP_MASK		0xff
 
-enum {
-	/* SMM handler area. */
-	SMM_SUBREGION_HANDLER,
-	/* SMM cache region. */
-	SMM_SUBREGION_CACHE,
-	/* Chipset specific area. */
-	SMM_SUBREGION_CHIPSET,
-	/* Total sub regions supported. */
-	SMM_SUBREGION_NUM,
-};
-
-/*
- * Fills in the arguments for the entire SMM region covered by chipset
- * protections. e.g. TSEG.
- */
-void smm_region_info(void **start, size_t *size);
-/*
- * Fills in the start and size for the requested SMM subregion. Returns
- * 0 on success, < 0 on failure.
- */
-int smm_subregion(int sub, void **start, size_t *size);
 void domain_enable_resources(struct device *dev);
 void domain_set_resources(struct device *dev);
 void fam15_finalize(void *chip_info);
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index 7c855bb1e1..8eb2e39883 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -19,6 +19,7 @@
 #include <stdint.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cbmem.h>
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 000d100fa3..4f38dbf138 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -19,6 +19,7 @@
 #include <arch/acpi.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <cpu/amd/mtrr.h>
 #include <cbmem.h>
 #include <commonlib/helpers.h>