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| author | John Zhao <john.zhao@intel.com> | 2020-08-14 21:18:27 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-08-18 15:57:50 +0000 |
| commit | 90e56267cf158af3d692b709f7f41120130234a4 (patch) | |
| tree | ebdb95dd9a905662fae56065a28f87cc442b0f58 /src/soc/amd | |
| parent | aa902036d0cc8dd48a36fd7cf5fd8e22930b7afd (diff) | |
mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpd
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1) without internal pull-down which wrongly presents HPD interrupts.
DP_HPD had been removed for EVT design as those events are through eSPI.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.
BUG=b:162566436
TEST=Booted to kernel and verified no kernel HPD pins assertion message
on Volteer EVT board.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia3245741b776b75073d2b43d36c8ea40b476b3ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44501
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd')
0 files changed, 0 insertions, 0 deletions