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authorFelix Held <felix-coreboot@felixheld.de>2023-08-09 19:28:39 +0200
committerMartin L Roth <gaumless@gmail.com>2023-08-15 14:56:11 +0000
commit8f0075c37924fc3be82b226d13a5e522eea9f795 (patch)
treed9f701380a1bd43347a79d7ac6ea8f0a557b3178 /src/soc/amd
parent38880d236fd97e3bdf61234363bc4cd7e9869870 (diff)
nb,soc/amd/*/northbridge: use mmio_range to add IOAPIC2 resources
Instead of open coding this, use the mmio_range helper function to tell the resource allocator about the northbridge's IOAPIC's MMIO. This change sets the IORESOURCE_RESERVE and IORESOURCE_STORED bits in the resource flags that weren't set before, but mmio_range is already used elsewhere for similar purposes. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id66a73cdb22fd551e4359914ba5513313dcc3193 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/stoneyridge/northbridge.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index ecdbe4fee9..081bc1f47d 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -59,7 +59,6 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index,
static void read_resources(struct device *dev)
{
unsigned int idx = 0;
- struct resource *res;
/* The northbridge has no PCI BARs implemented, so there's no need to call
pci_dev_read_resources for it */
@@ -72,10 +71,7 @@ static void read_resources(struct device *dev)
mmconf_resource(dev, idx++);
/* NB IOAPIC2 resource */
- res = new_resource(dev, idx++); /* IOAPIC2 */
- res->base = IO_APIC2_ADDR;
- res->size = 0x00001000;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ mmio_range(dev, idx++, IO_APIC2_ADDR, 0x1000);
}
static void set_resource(struct device *dev, struct resource *res, u32 nodeid)