summaryrefslogtreecommitdiff
path: root/src/soc/amd
diff options
context:
space:
mode:
authorMaximilian Brune <maximilian.brune@9elements.com>2024-08-09 12:43:16 +0200
committerMarshall Dawson <marshalldawson3rd@gmail.com>2024-09-26 21:53:15 +0000
commit643b28f5181174fea3aa0f1a2972474c75545a37 (patch)
tree5e8af0b11ab36a013a82ea0e4f1623ef181b9227 /src/soc/amd
parentbd1887ddd4fa59143c25616b4f2fbdb1ca68f823 (diff)
soc/amd/glinda/chipset.cb: Add missing devices
Source: Document 57254 Change-Id: I9675d45eba257e52d9a870a4cc153b925267f840 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/glinda/chipset.cb13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb
index 5a6541feb3..6e23c2d4c2 100644
--- a/src/soc/amd/glinda/chipset.cb
+++ b/src/soc/amd/glinda/chipset.cb
@@ -10,6 +10,9 @@ chip soc/amd/glinda
device pci 00.2 alias iommu off ops amd_iommu_ops end
device pci 01.0 on end # Dummy device function
+ device pci 01.1 alias usb4_pcie_bridge_0 off end
+ device pci 01.2 alias usb4_pcie_bridge_1 off end
+ device pci 01.3 alias usb4_pcie_bridge_2 off end
device pci 02.0 on end # Dummy device function, do not disable
device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end
@@ -18,6 +21,13 @@ chip soc/amd/glinda
device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end
device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end
device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end
+ device pci 03.0 on end # Dummy device function, do not disable
+ device pci 03.1 alias gpp_bridge_3_1 off ops amd_external_pcie_gpp_ops end
+ device pci 03.2 alias gpp_bridge_3_2 off ops amd_external_pcie_gpp_ops end
+ device pci 03.3 alias gpp_bridge_3_3 off ops amd_external_pcie_gpp_ops end
+ device pci 03.4 alias gpp_bridge_3_4 off ops amd_external_pcie_gpp_ops end
+ device pci 03.5 alias gpp_bridge_3_5 off ops amd_external_pcie_gpp_ops end
+ device pci 03.6 alias gpp_bridge_3_6 off ops amd_external_pcie_gpp_ops end
device pci 08.0 on end # Dummy device function, do not disable
device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A
@@ -47,6 +57,7 @@ chip soc/amd/glinda
device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
ops amd_internal_pcie_gpp_ops
device pci 0.0 on end # dummy, do not disable
+ device pci 0.1 alias npu off end # Neural Processing Unit (NPU)
end
device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
@@ -109,6 +120,8 @@ chip soc/amd/glinda
end
end
end
+ device pci 0.5 alias usb4_router_0 off end
+ device pci 0.6 alias usb4_router_1 off end
end
device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function