diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-04-22 23:25:28 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-26 17:55:00 +0000 |
| commit | 43d8eca2ba4913dab91b65507e4e42f5725b9b2c (patch) | |
| tree | d89fdcc578f1eb6bcbdbd50d6ebcc2118b57aac9 /src/soc/amd | |
| parent | 86056683a5bc4f8fd0b63aa665e05dda566791e1 (diff) | |
soc/amd/picasso/mca: use MCAX registers instead of legacy MCA
This patch also adds the additional 10 MCAX registers to the BERT MSR
error record.
BUG=b:186038401
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I31912d3b3e77e905f64b6143042f5e7f73db7407
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/picasso/mca.c | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 0fd2d17cb5..aab95ca48a 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -9,6 +9,9 @@ #include <arch/bert_storage.h> #include <cper.h> +/* MISC4 is the last used register in the MCAX banks of Picasso */ +#define MCAX_USED_REGISTERS_PER_BANK (MCAX_MISC4_OFFSET + 1) + struct mca_bank { int bank; msr_t ctl; @@ -36,8 +39,9 @@ static inline size_t mca_report_size_reqd(void) /* Context of MCG_CAP, MCG_STAT, MCG_CTL */ size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 3); - /* Context of MCi_CTL, MCi_STATUS, MCi_ADDR, MCi_MISC */ - size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 4); + /* Context of CTL, STATUS, ADDR, MISC0, CONFIG, IPID, SYND, RESERVED, DESTAT, DEADDR, + MISC1, MISC2, MISC3, MISC4 */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, MCAX_USED_REGISTERS_PER_BANK); /* Context of CTL_MASK */ size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 1); @@ -118,8 +122,8 @@ static void build_bert_mca_error(struct mca_bank *mci) ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); if (!ctx) goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, - IA32_MC0_CTL + (mci->bank * 4), 4); + ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCAX_CTL_MSR(mci->bank), + MCAX_USED_REGISTERS_PER_BANK); if (!ctx) goto failed; ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCA_CTL_MASK_MSR(mci->bank), 1); @@ -144,7 +148,7 @@ static const char *const mca_bank_name[] = { "L3 cache unit" }; -/* Check the Legacy Machine Check Architecture registers */ +/* Check the Machine Check Architecture Extension registers */ void check_mca(void) { int i; @@ -157,7 +161,7 @@ void check_mca(void) if (is_warm_reset()) { for (i = 0 ; i < num_banks ; i++) { - mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); + mci.sts = rdmsr(MCAX_STATUS_MSR(i)); if (mci.sts.hi || mci.sts.lo) { int core = cpuid_ebx(1) >> 24; @@ -167,13 +171,13 @@ void check_mca(void) printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", i, mci.sts.hi, mci.sts.lo); - mci.addr = rdmsr(MC0_ADDR + (i * 4)); + mci.addr = rdmsr(MCAX_ADDR_MSR(i)); printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", i, mci.addr.hi, mci.addr.lo); - mci.misc = rdmsr(MC0_MISC + (i * 4)); + mci.misc = rdmsr(MCAX_MISC0_MSR(i)); printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", i, mci.misc.hi, mci.misc.lo); - mci.ctl = rdmsr(IA32_MC0_CTL + (i * 4)); + mci.ctl = rdmsr(MCAX_CTL_MSR(i)); printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", i, mci.ctl.hi, mci.ctl.lo); mci.cmask = rdmsr(MCA_CTL_MASK_MSR(i)); @@ -192,5 +196,5 @@ void check_mca(void) mci.sts.lo = 0; mci.sts.hi = 0; for (i = 0 ; i < num_banks ; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), mci.sts); + wrmsr(MCAX_STATUS_MSR(i), mci.sts); } |