diff options
| author | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2022-08-22 17:30:00 -0500 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-08-25 01:01:29 +0000 |
| commit | 32bb6b6500eab66658928c5930e899577e5a44b8 (patch) | |
| tree | 906e285baaf42dbce23b7854a615c78f3acb9b5a /src/soc/amd | |
| parent | bb9d106eab6212229fb1d6d4645f93bb883850ac (diff) | |
soc/amd/common/fsp/dmi: Translate DRAM speeds for (LP)DDR5
Hook up newly-added method to convert from frequency to MT/s so that
boards which use (LP)DDR5 report their capability properly.
BUG=b:239000826
TEST=build/boot google/skyrim, verify SMBIOS Type 17 table reports
DRAM speeds correctly.
Change-Id: I694b6c227a8d8fb40c897053808bc79df330ed0c
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66954
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/fsp/dmi.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/common/fsp/dmi.c b/src/soc/amd/common/fsp/dmi.c index b500155a03..872417ba44 100644 --- a/src/soc/amd/common/fsp/dmi.c +++ b/src/soc/amd/common/fsp/dmi.c @@ -16,6 +16,7 @@ #include <dmi_info.h> #include <device/dram/ddr4.h> #include <device/dram/lpddr4.h> +#include <device/dram/ddr5.h> /** * Convert DDR clock speed (based on memory type) in MHz to the standard reported speed in MT/s @@ -27,6 +28,9 @@ static uint16_t ddr_speed_mhz_to_reported_mts(uint16_t ddr_type, uint16_t speed) return ddr4_speed_mhz_to_reported_mts(speed); case MEMORY_TYPE_LPDDR4: return lpddr4_speed_mhz_to_reported_mts(speed); + case MEMORY_TYPE_DDR5: + case MEMORY_TYPE_LPDDR5: + return ddr5_speed_mhz_to_reported_mts(speed); default: printk(BIOS_ERR, "Unknown memory type %x\n", ddr_type); return 0; |