device/resource: Add _kb postfix for resource allocators

There is a lot of going back-and-forth with the KiB arguments, start
the work to migrate away from this.

Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

9 files changed, 36 insertions, 36 deletions

diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c
index 1381df3fd6..075f1a1f76 100644
--- a/src/soc/amd/cezanne/root_complex.c
+++ b/src/soc/amd/cezanne/root_complex.c
@@ -118,27 +118,27 @@ static void read_resources(struct device *dev)
 	   pci_dev_read_resources for it */
 
 	/* 0x0 - 0x9ffff */
-	ram_resource(dev, idx++, 0, 0xa0000 / KiB);
+	ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);
 
 	/* 0xa0000 - 0xbffff: legacy VGA */
-	mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
+	mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
 
 	/* 0xc0000 - 0xfffff: Option ROM */
-	reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
+	reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
 
 	/* 1MiB - bottom of DRAM reserved for early coreboot usage */
-	ram_resource(dev, idx++, (1 * MiB) / KiB,
+	ram_resource_kb(dev, idx++, (1 * MiB) / KiB,
 		     (early_reserved_dram_start - (1 * MiB)) / KiB);
 
 	/* DRAM reserved for early coreboot usage */
-	reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB,
+	reserved_ram_resource_kb(dev, idx++, early_reserved_dram_start / KiB,
 		(early_reserved_dram_end - early_reserved_dram_start) / KiB);
 
 	/*
 	 * top of DRAM consumed early - low top usable RAM
 	 * cbmem_top() accounts for low UMA and TSEG if they are used.
 	 */
-	ram_resource(dev, idx++, early_reserved_dram_end / KiB,
+	ram_resource_kb(dev, idx++, early_reserved_dram_end / KiB,
 		     (mem_usable - early_reserved_dram_end) / KiB);
 
 	mmconf_resource(dev, idx++);
@@ -162,9 +162,9 @@ static void read_resources(struct device *dev)
 			continue; /* Done separately */
 
 		if (res->type == EFI_RESOURCE_SYSTEM_MEMORY)
-			ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
+			ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
 		else if (res->type == EFI_RESOURCE_MEMORY_RESERVED)
-			reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
+			reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
 		else
 			printk(BIOS_ERR, "failed to set resources for type %d\n",
 					res->type);
diff --git a/src/soc/amd/cezanne/uart.c b/src/soc/amd/cezanne/uart.c
index cf535d7aec..7917ebd195 100644
--- a/src/soc/amd/cezanne/uart.c
+++ b/src/soc/amd/cezanne/uart.c
@@ -87,7 +87,7 @@ static void uart_enable(struct device *dev)
 
 static void uart_read_resources(struct device *dev)
 {
-	mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4);
+	mmio_resource_kb(dev, 0, dev->path.mmio.addr / KiB, 4);
 }
 
 struct device_operations cezanne_uart_mmio_ops = {
diff --git a/src/soc/amd/common/block/i2c/i2c.c b/src/soc/amd/common/block/i2c/i2c.c
index 2a81286019..30e02ee07d 100644
--- a/src/soc/amd/common/block/i2c/i2c.c
+++ b/src/soc/amd/common/block/i2c/i2c.c
@@ -117,7 +117,7 @@ void i2c_soc_init(void)
 
 static void i2c_read_resources(struct device *dev)
 {
-	mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4);
+	mmio_resource_kb(dev, 0, dev->path.mmio.addr / KiB, 4);
 }
 
 struct device_operations soc_amd_i2c_mmio_ops = {
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 60c85b9ce4..0eda7f2fd8 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -117,7 +117,7 @@ static void lpc_read_resources(struct device *dev)
 		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	/* Add a memory resource for the SPI BAR. */
-	fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / KiB, 1,
+	fixed_mem_resource_kb(dev, 2, SPI_BASE_ADDRESS / KiB, 1,
 			IORESOURCE_SUBTRACTIVE);
 
 	res = new_resource(dev, 3); /* IOAPIC */
diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c
index 73a50a915a..ccf1c45fcd 100644
--- a/src/soc/amd/picasso/root_complex.c
+++ b/src/soc/amd/picasso/root_complex.c
@@ -118,25 +118,25 @@ static void read_resources(struct device *dev)
 	   pci_dev_read_resources for it */
 
 	/* 0x0 - 0x9ffff */
-	ram_resource(dev, idx++, 0, 0xa0000 / KiB);
+	ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);
 
 	/* 0xa0000 - 0xbffff: legacy VGA */
-	mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
+	mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
 
 	/* 0xc0000 - 0xfffff: Option ROM */
-	reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
+	reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
 
 	/* 1MB - bottom of DRAM reserved for early coreboot usage */
-	ram_resource(dev, idx++, (1 * MiB) / KiB,
+	ram_resource_kb(dev, idx++, (1 * MiB) / KiB,
 		     (early_reserved_dram_start - (1 * MiB)) / KiB);
 
 	/* DRAM reserved for early coreboot usage */
-	reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB,
+	reserved_ram_resource_kb(dev, idx++, early_reserved_dram_start / KiB,
 		(early_reserved_dram_end - early_reserved_dram_start) / KiB);
 
 	/* top of DRAM consumed early - low top usable RAM
 	 * cbmem_top() accounts for low UMA and TSEG if they are used. */
-	ram_resource(dev, idx++, early_reserved_dram_end / KiB,
+	ram_resource_kb(dev, idx++, early_reserved_dram_end / KiB,
 		     (mem_usable - early_reserved_dram_end) / KiB);
 
 	mmconf_resource(dev, idx++);
@@ -160,9 +160,9 @@ static void read_resources(struct device *dev)
 			continue; /* Done separately */
 
 		if (res->type == EFI_RESOURCE_SYSTEM_MEMORY)
-			ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
+			ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
 		else if (res->type == EFI_RESOURCE_MEMORY_RESERVED)
-			reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
+			reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
 		else
 			printk(BIOS_ERR, "failed to set resources for type %d\n",
 					res->type);
diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c
index 1ffb2fdf70..5763a5b17c 100644
--- a/src/soc/amd/picasso/uart.c
+++ b/src/soc/amd/picasso/uart.c
@@ -105,7 +105,7 @@ static void uart_enable(struct device *dev)
 
 static void uart_read_resources(struct device *dev)
 {
-	mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4);
+	mmio_resource_kb(dev, 0, dev->path.mmio.addr / KiB, 4);
 }
 
 struct device_operations picasso_uart_mmio_ops = {
diff --git a/src/soc/amd/sabrina/root_complex.c b/src/soc/amd/sabrina/root_complex.c
index 8f91b2af81..76ed7650e8 100644
--- a/src/soc/amd/sabrina/root_complex.c
+++ b/src/soc/amd/sabrina/root_complex.c
@@ -120,27 +120,27 @@ static void read_resources(struct device *dev)
 	   pci_dev_read_resources for it */
 
 	/* 0x0 - 0x9ffff */
-	ram_resource(dev, idx++, 0, 0xa0000 / KiB);
+	ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);
 
 	/* 0xa0000 - 0xbffff: legacy VGA */
-	mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
+	mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
 
 	/* 0xc0000 - 0xfffff: Option ROM */
-	reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
+	reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
 
 	/* 1MiB - bottom of DRAM reserved for early coreboot usage */
-	ram_resource(dev, idx++, (1 * MiB) / KiB,
+	ram_resource_kb(dev, idx++, (1 * MiB) / KiB,
 		     (early_reserved_dram_start - (1 * MiB)) / KiB);
 
 	/* DRAM reserved for early coreboot usage */
-	reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB,
+	reserved_ram_resource_kb(dev, idx++, early_reserved_dram_start / KiB,
 		(early_reserved_dram_end - early_reserved_dram_start) / KiB);
 
 	/*
 	 * top of DRAM consumed early - low top usable RAM
 	 * cbmem_top() accounts for low UMA and TSEG if they are used.
 	 */
-	ram_resource(dev, idx++, early_reserved_dram_end / KiB,
+	ram_resource_kb(dev, idx++, early_reserved_dram_end / KiB,
 		     (mem_usable - early_reserved_dram_end) / KiB);
 
 	mmconf_resource(dev, idx++);
@@ -164,9 +164,9 @@ static void read_resources(struct device *dev)
 			continue; /* Done separately */
 
 		if (res->type == EFI_RESOURCE_SYSTEM_MEMORY)
-			ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
+			ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
 		else if (res->type == EFI_RESOURCE_MEMORY_RESERVED)
-			reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
+			reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
 		else
 			printk(BIOS_ERR, "Error: failed to set resources for type %d\n",
 					res->type);
diff --git a/src/soc/amd/sabrina/uart.c b/src/soc/amd/sabrina/uart.c
index 0ffdacf792..981e6f0b60 100644
--- a/src/soc/amd/sabrina/uart.c
+++ b/src/soc/amd/sabrina/uart.c
@@ -114,7 +114,7 @@ static void uart_enable(struct device *dev)
 
 static void uart_read_resources(struct device *dev)
 {
-	mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4);
+	mmio_resource_kb(dev, 0, dev->path.mmio.addr / KiB, 4);
 }
 
 struct device_operations sabrina_uart_mmio_ops = {
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 2166ef477f..a47ef25e72 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -396,23 +396,23 @@ void domain_read_resources(struct device *dev)
 	pci_domain_read_resources(dev);
 
 	/* 0x0 -> 0x9ffff */
-	ram_resource(dev, idx++, 0, 0xa0000 / KiB);
+	ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);
 
 	/* 0xa0000 -> 0xbffff: legacy VGA */
-	mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
+	mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
 
 	/* 0xc0000 -> 0xfffff: Option ROM */
-	reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
+	reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
 
 	/*
 	 * 0x100000 (1MiB) -> low top usable RAM
 	 * cbmem_top() accounts for low UMA and TSEG if they are used.
 	 */
-	ram_resource(dev, idx++, (1 * MiB) / KiB,
+	ram_resource_kb(dev, idx++, (1 * MiB) / KiB,
 			(mem_useable - (1 * MiB)) / KiB);
 
 	/* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */
-	reserved_ram_resource(dev, idx++, mem_useable / KiB,
+	reserved_ram_resource_kb(dev, idx++, mem_useable / KiB,
 					(tom.lo - mem_useable) / KiB);
 
 	/* If there is memory above 4GiB */
@@ -424,12 +424,12 @@ void domain_read_resources(struct device *dev)
 			high_mem_useable = ((uint64_t)high_tom.lo |
 						((uint64_t)high_tom.hi << 32));
 
-		ram_resource(dev, idx++, (4ull * GiB) / KiB,
+		ram_resource_kb(dev, idx++, (4ull * GiB) / KiB,
 				((high_mem_useable - (4ull * GiB)) / KiB));
 
 		/* High top usable RAM -> high top RAM */
 		if (uma_base >= (4ull * GiB)) {
-			reserved_ram_resource(dev, idx++, uma_base / KiB,
+			reserved_ram_resource_kb(dev, idx++, uma_base / KiB,
 						uma_size / KiB);
 		}
 	}